WNMD2160 Introduction

Low-power mos is a planar structure. The power mos used on electric vehicles is a three-dimensional structure. The mos tube we have seen is actually composed of thousands of small mos tubes in parallel. You may think that one or a few bad moss should easily appear in thousands of small mos. In fact, it is not that easy. , the current manufacturing process basically guarantees the high consistency of various parameters of these small units.

According to the carrier of the conduction channel, it can be divided into N channel and P channel. Assuming that the carriers of the conductive channel are electrons, it is called an N-channel; assuming that the carriers are holes, it is called a P-channel. A MOS tube is a semiconductor device in which unipolar carriers participate in conduction.

AP9926GM_RU30D8HCGTR

WNMD2160

MOS tube is a metal (Metal)-oxide (Oxide)-semiconductor (Semiconductor) field effect transistor, or metal-insulator (Insulator)-semiconductor. .

NCE3019AS NCE3045G NCE3400AY NCE30ND07S NCE8601B.

G: gate gate; S: source source; D: drain drain. Such devices are considered symmetrical. Generally, it is a metal-oxide-semiconductor field effect transistor, or a metal-insulator-semiconductor. The source (source) and drain (depletion layer) of the MOS tube can be reversed, and they are all N-type regions formed in the P-type backgate. In most cases, these two regions are the same, even if the two ends are reversed, it will not affect the performance of the device.

There are three parasitic capacitance parameters in the MOS tube specification, namely: input capacitance Ciss, output capacitance Coss, and reverse transfer capacitance Crss. What do the three capacitance parameters represent in the body of the tube? How did it form? .

AP9926GM_RU30D8HCGTR

WNMD2160

NCE3008M NCE3010S NCE3011E NCE30D0808J NCE3018AS.

The structure of the MOSFET shown in the figure is not suitable for use in high-power applications for two reasons. On the one hand, the three electrodes of the low-power MOSFET are on one plane, the channel cannot be made very short, and the channel resistance is large. On the other hand, the conductive channel is composed of surface induced charges, and the channel current is the surface current. To increase the current capacity, it is necessary to increase the chip area. Such a structure is unlikely to achieve a large current. .

The N-channel enhancement mode MOS transistor uses a low-doped P-type semiconductor as the substrate, and forms two heavily doped N+ regions on the substrate by a dispersed method, and then generates a very thin one on the P-type semiconductor. A silicon dioxide insulating layer, and then photolithography is used to etch away the silicon dioxide layer on the upper end of the two heavily doped N+ regions, exposing the N+ regions, and finally on the outer surface of the two N+ regions and the two between them. The surface of silicon oxide is sprayed with a layer of metal film by evaporation or sputtering. These three metal films constitute the three electrodes of the MOS tube, which are called source (S), gate (G) and drain (D) respectively. .

When the applied forward voltage increases, the concentration of unbalanced minority carriers increases and the concentration gradient also increases, and when the applied voltage decreases, the change is opposite. Diffusion capacitance: When a forward voltage is applied, the non-equilibrium minority carrier concentration near the interface of the depletion layer is high, far from the non-equilibrium minority carrier concentration is low, and the concentration gradually decays from high to 0 until it reaches zero. The process of charge accumulation and release in this phenomenon is the same as that of capacitor charging and discharging, which is called diffusion capacitance.

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NCE20ND06 NCE2008N NCE2312 NCE2312A NCE8205A.

. MOS tube NCE3401 is a -30V drain-source voltage, 4.2A current, P-channel MOS tube in SOT-23 package.

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