Eight low RDSON data output (at 25 ° C at IO 1A is 0.5 , VCC 5V ± 5%)

8 -bit serial input data (SPI)

8 -bit serial diagnosis output

overload and opening conditions

Output short circuit protection

ChipenableSelectFunction (low level valid)

Each output each output的内部35V夹持

与另一个八进制级联

低静态电流（最大10mA）

组件电源SO20

说明[ 123]

L9822N is an octagonal low -voltage -side solenoid valve driver. The multi -power BCD technology is suitable for the mobile environment of the lights, relays and solenoid valves. The output of DMOS exceeds L9822N with very low power consumption. The data is transmitted to the device serial peripheral interface (SPI) protocol. L9822N has the function of output status monitoring function.

Dilament

Device ground. This logical circuit and power output -level grounding device.

Reset

asynchronous reset L9822nsp output level, parallel lock depositors and displacement registers. This pin is in a low activation state and cannot maintain a floating state. The power -powered function can connect the pin to the VCC to the VCC with an external capacitor through an external resistor. Chief engineer chip enable. The data transmits from the shift register to the output end of the signal rising edge. The decline of the signal of the settings shifting register output voltage detection level comes from the output level. The output drive of the SO pin is enabled when this pin is low. So serial output. This pin is a shift register. When the CE is high, it is three -state. A The data position on this tube is high. It means that the special output is high. The low data bit on the pin means that the output is low. The diagnostic data provided by L9822 will be performed by comparing the serial output position with the previous one to compare the serial input position.

Silicon

Serial input. This pin is serial data input. The climax is PIN, and a PARTICULARROUTPUTTBEOFF will be programmed, which will open it with low pressure.

Serial clock. This pin is a time -off register. The new data will appear in each rising data of this pin along the new data will be locked to every SLK #39; s Fal Ling Edge to the displacement register.

Output 00-07

ElectricityThe source output pins input and output position correspond to 07 bits. First, the bus and 00 through the SPI are the last class. The output has a current limitation and the voltage induction function used for fault indications and protection. The rated load current of these output is 500 mAh. The output is also set to about 36V on the board, which is used to inductive load re -cycle current.

Electrical features (VCC 5V ± 5%. Tj - 40 to 125 ° C; unless there are other regulations)

Functional description

The working power of the equipment output at L9822ndmos is very low. The output stage of 8 1 RDSON DMOS driver has a transient protection circuit. Each channel is independently controlled by the output lock and the public reset line. Low -circuit protection and DC electricity of the driver, as well as resistance loads such as solenoid valves, lights and relays. Data is transmitted to the device protocol through these serial interfaces (SPI). The circuit is stored in the internal register through the serial input receiving 8 -bit serial data (SI) to control the output driver. Serial output (SO) provides 8 diagnostic data bits that represent voltage levels at the drive output end. This makes the microprocessor diagnose the condition of the output drive.

The output saturation voltage can be reset to the specific river line through the fault. This circuit can also be counted with other octagonal drives to block 8 multiple data. When the chip is enabled (CE), the device line is low. In addition, the (SO) is placed in a three -state mode to cancel the selection device. The active effect of the voltage level of the negative edge (CE) transmission drive on the mobile register and (CE) will be locked on the two drivers from the new data of the shift register. When the CE is low, the data bit is contained in the SCLK input in the SCLK input in the SI when each data bit is locked in the shift to the displacement register negative migration.

Internal block explanation

The internal architecture of the device is based on three internal main blocks: an octagonal displacement register for dialogue with the SPI bus, an octagonal lock of the control bit of the control bit of the device, and an octagonal loading loading Drive program group.

Showing register

The displacement register has serial and parallel input and serial and parallel output. The serial input AC receives data from Spibus, and the serial output sends the data to the SPI bus at the same time. This parallel output is locked at the end of the lock of L9822N at the end of the data transmission. At the beginning of the data transmission cycle, the parallel input card diagnostic data is diagnosed to the shift register.

Parallel lock

Parallel lock depositors save the input data registration from shift. Then these data -driven output levels. The single register in the lock memory can be output during the overloaded failure condition. The entire lock is also cleared through the reset signal.

Output level

The output level provides active low -drive signals for 0.75A continuous load. The output is set to 36 volts inside, so that the induction induction transition is compromised when closed. Each output also has a voltage comparator B serving outputNode. If the voltage on this ON output pin exceeds 1.8V, that is, the fault assumption conditions are driven, and the specific -level lock reset will be driven to protect it. The time for this operation is as described below. These comparators also move to the displacement register. In addition, the COM Parators contains a internal drop -down current that will cause the battery indicator to indicate a low output voltage. If the output programming is closed, the output pins are opened. The timing data transmission diagram 2 shows the use of the SPI bus. CE-high-low transition Dang chip enable (CE) pin (CE) pin is pulled down. TheTri-StateSerialoutPut (SO) pin driver will make the CE lower time. At the edge of the CE pin, the diagnostic data comes from the voltage comparator in the output stage. If the specific output is high, a logical signal will be plugged into the displacement register. If the output is low, the logic zero will be the most important bit (07) here (07) to display the serial input (SI) pin. A zero -legged foot will program out one output, and one will turn off the programming output.

SCLK transition

Then the serial clock (SCLK) pin should be pulled out. At this point, the diagnostic level from the most important output (07) will appear at the highest point here that the 07 pin is higher than 1.8V. Then lower the SCLK pin to high. The new SO data will appear SCLK and the new SI data after each edge will be locked to the L9822N shift register on the decrease. Unlimited data can be shifted through the E-ViceShift register (input Si Pin and output the PIN) to allow other SPI device levels to connect to the chrysanthemum chain with L9822N.

CE low to high change

Once the data is moved to the last L9822nsp, CE sales should be raised. At the rising edge of the CE, the displacement register data is horizontal, and the output level will be driven by new data. The internal 160 μS delayed timer will also start (see Tuand) at the rising edge. During the 160μs period, the output will last for a period of time by the protection of analog restricted circuit due to faults. This reduced parts may flow immediately after overcoming Gao Yongliu. Once the delayed time has passed, the output voltage is to induced Valerachertorf through the comparator and any output with a volume greater than 1.8. It should be noted. Avoid file changes. TheSCLKINPUTIS is taken over by the Chief Executive to make SCLK pins high in the CE pin.

You can use the following methods to check the fault situationcondition.Enter the new control bytes.Wait for 160 microseconds to stabilize the output.Time on the same controller and observe the diagnostic data of the device output.The diagnostic level should be poured in the first time.Any difference will open the output to the error.If the output is 0 and 1 as the diameter of the output, the output PIN is still very high and there are short circuit or overload.If the output is closed when the input is 1, the output of a zero as a diagnosis is returned. The height of the output pins must be floated. Therefore, there is a way to open the way to that output.

Figure 1: byte timing of the asynchronreset.