Features

14 -bit dual transmission digital mode converter (DAC)

200 msps update rate

single Power: 3.0 V to 3.6 v

High -free and non -boring dynamic range (sfdr): 5 mHz at 84 dbc

IMD3): 79 dbc

WCDMA adjacent channel leakage (ACLR) at 15.1 MHz and 16.1 MHz (ACLR): baseband 78 db

WCDMA ACLR: 30.72 MHz is 73 db

Independent or single-resistance gain control

dual data or cross data

1.2-v Standards

Low power: 330 MW

Power off mode: 9 mw

Packaging: 48 pin thin square flat flat flat flat flat flat Packaging (TQFP)

Application

Honeycomb base station transmission channel

—CDMA: W-CDMA, CDMA2000, IS-95

]-Tdma: GSM, IS-136, Edge/UWC-136

Medical/Test Instruments

Any waveform generator (ARB)

[ [ 123] Direct digital synthesis (DDS)

cable modem terminal system (CMTS)

Explanation

DAC5672

Yes A single piece, dual -channel, 14 -bit, high -speed DAC, with the internal reference voltage.

The update rate of DAC5672 is as high as 200 milliseconds/second. It has excellent dynamic performance, high gain and offset matching characteristics, suitable for I/Q baseband or direct intermediate frequency communication application.

Each DAC has high impedance, differential current output, and is suitable for single -end or differential analog output configuration. The external resistor allows the full -scale output current of each DAC alone or together, usually between 2 mA and 20 mA. The accurate in -chip benchmark voltage is compensated by temperature and provides a stable 1.2V reference voltage. Alternatively, you can use external reference.

DAC5672 has two 14 -bit parallel input ports with separate clocks and data locks. forIncrease flexibility, when working in the interwoven mode, the DAC5672 also supports the data for each DAC on one port.

DAC5672 is specifically designed for coupling output for differential transformers with a differential transformer with a 50Ω dual -end load. For the 20 mAh -full -standard output current, it supports the 4: 1 impedance ratio (generated 4 DBM output power) and the 1: 1 impedance ratio transformer (-2 DBM output power). DAC5672 is encapsulated by 48 -pin TQFP. The pin compatibility between members of the series provides 12 -bit (DAC5662) and 14 -bit (DAC5672) resolution. In addition, DAC5672 is compatible with DAC2904 and AD9767 dual DAC pins. The feature is characterized by the industrial temperature range of -40 ° C to 85 ° C.

Figure Figure

Typical features [

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Digital input and timing

Digital input

DAC5672 data input port receiving standard coding, data bit DA13, and data bit DA13, and DB13 is the highest effective position (MSB). The converter output supports a clock rate of up to 200 millisecond/second. The best performance is usually achieved through symmetrical writing and clock duty cycle; however, as long as the timing specification is met, the duty cycle may change. Similarly, settings and maintenance time can be selected within its specified restrictions.

All digital inputs in DAC5672 are compatible with CMOS. Figure 17 and 18 show the schematic diagram of the equivalent CMOS digital input of DAC5672. 14 -digit data input follows the binary coding scheme. DAC5672 Design is used to use digital sources (DVD)

Input interface

DAC5672 with two working modes for choosing a pattern pins, as shown below Show:

For the dual bus input mode, the device is basically composed of two independent DACs. Each DAC has its own independent data input bus, clock input and data writing signal (data lock).

In a single bus cross mode, the data must be displayed on the bus in the A channel. In this mode, the B -channel input bus is not used. The clock and writing input are now shared by two DACs.

Double bus data interface and timing

In the dual bus mode, the pattern pins are connected to the DVD. Two converter channels in DAC5672 are parallel data of two independent 14 -bit parallel dataPort composition. Each DAC channel is controlled by its own groups (WRTA, WRTB) and clocks (CLKA, CLKB). WRTA/B control channel input locks, CLKA/B control DAC locks. The data is first loaded by the rising edge of the WRTA/B line to the input lock.

Internal data transmission requires correct writing and clock input sequence, because the clock domain with the same cycle (but may be different) is actually input to DAC5672. This is the input defined by the minimum requirements between the clock ascending and writing rising edges. This essentially means that the rising edge of CLKA/B must appear at the same time or before the WRTA/B signal rising edge. If the clock rising edge occurs after the rising edge is written, it must be delayed at least 2 ns. Note that when the clock and the writing input are connected to the outside, these conditions are met. Note that all specifications are measured in the case of the WRTA/B and CLKA/B lines.

Single bus cross -data interface and timing

In the single bus staggered mode, the pattern pins are connected to DGND. Figure 20 shows the sequence diagram. In staggered mode, A -channel and B passage shared input (WRTIQ) and update clocks (CLKIQ and internal CLKDACIQ). Multi -way reuse logic orientation is directed to the input word on the A channel into the bus to input the lock memory (SELECTIQ high) or the B channel input lock (SELECTIQ low). When the Selectiq is high, the value in the data B channel lock memory is maintained by reappearing the input data output data. When the Selectiq is low, the data value in the A -channel lock memory is kept by input the display lock output data to it.

In the staggered mode, the A -channel input data rate is twice the DAC core update rate. In the dual bus mode, it is important to maintain the correct order of writing and clock input. The edge trigger locks the A -channel and B channel input in the rising edge of the input (WRTIQ). The data shows the A and B-DAC memory in the following drop in the input. Before entering the DAC5672 clock to the DAC memory, divide it to coefficient 2.

The correct pairing of A channel and B channel data is completed by resetiq. In the staggered mode, the clock input CLKIQ is divided by the second, which will be converted into the non -confirmed relationship between CLKIQ and CLKDACIQ rising edges. However, ResetIQ ensures that the correct position of the CLKDACIQ rising along the data of the data input at the DAC memory input is determined. When ReseTiq is high, CLKDACIQ is disabled (low).

Application information

Operation theory

The architecture of DAC5672 uses current control technology to achieve fast switching and high update rates. The core component in a single DAC is a segmented current source array, which is designed to provide a full range output current of up to 20 mAh. The internal decoder addresss the differential current switch at the DAC update, and forms a corresponding output current by turning all current to output and node iOUT1 or IOUT2. Compared with single -end operations, complementary output provides differential output signals, and increases dynamic performance by reducing the increasing amplitude of the occurrence of occasional harmonic, co -mode signals (noise), and peak -to -peak output signals.

The segmented structure has significantly reduced the fault energy and improved the dynamic performance (SFDR) and DNL. The current output maintains a very high output impedance greater than 300 k u0026#8486;

When the pin 42 (GSET) is high (synchronous gain setting mode), the full standard output current of the two DACs is from internal reference voltage (1.2 v) and connected to biasj u0026#273; A The ratio of the resistor (RSET) determines. When the GSET is low (independent gain setting mode), the percentage output current of each DAC is determined by the internal reference voltage (1.2 V) and the independent external resistor (RSET) connected to the BIASJ_A and BIASJ_B. Iref is multiplied by the internal multiplier coefficient 32 to generate an effective DAC output current, with a range of 2 mA to 20 mA, depending on the value of RSET.

DAC5672 is divided into two parts: digital and analog, each part is powered by its own power supply. That digital part includes the input lock and decoding logic of the edge, while the analog part includes the simulation part includes the current source array and its related switches and reference circuits.

DAC transmission function

Each DAC in DAC5672 has a set of complementary current outputs, iOUT1 and IOUT2.满标度输出电流IOUTFS是两个互补输出电流的总和：

单个输出电流取决于DAC代码，可以表示为：

[123 ]

The code is the decimal representation of the DAC data input word. In addition, IOUTFS is a reference current Iref function, which is determined by the reference voltage and external setting resistor (RSET).

In most cases, the complementary output drive resistor load or terminal transformer. The signal voltage of each output terminal is based on:

The load resistance value is limited by the DAC5672 output compliance specification. To maintain the specified linear performance, the voltage of iOut1 and IOUT2 u200bu200bmust not exceed the maximum allowable compliance range.

The total differential output voltage is:

Simulation output

DAC5672 provides two complementary current outputs, iOUT1 and IOUT2. The simplified circuit of the simulation output level of differential topology is shown in Figure 21. The output impedance of iOUT1 and IOUT2 u200bu200bis combined by the parallel switch, current source and related parasitic capacitors.

The signal voltage of the signal voltage generated at the two outputs may be restricted by the positive and negative convergence. The negative limit-1V is given by the breakdown voltage of the CMOS process, and exceeding this limit will damage the reliability of the DAC5672 (even cause permanent damage). When the full margin output is set to 20 mA, the positive rules are equal to 1.2 volts. Please note that for the selected output current iOutfs u003d 2 mAh, the scope of compliance is reduced to about 1 volt. It must be noted that the configuration of the DAC5672 does not exceed the scope of compliance to avoid degeneration of distortion performance and integral linearity.

The best distortion performance is usually implemented at a maximum full -scale output signal restricted at about 0.5VPP. This is the case of the 50Ω dual -end load and the 20 MA full marking output current. By selecting the right transformer and maintaining the best voltage level of iOUT1 and IOUT2, various loads can adapt to the output of DAC5672. In addition, the use of differential output configurations with transformers can help obtain excellent distortion performance. Common model errors, such as occasional harmonics or noise, can be greatly reduced. This is especially true in the case of high output frequency.

For applications that require the best distortion and noise performance, it is recommended to choose a full standard output of 20 mAh. For applications that require low power consumption, you can consider the low full range range of 2 mA, but it can tolerate the slight decrease in performance level.

Output configuration

The current output of DAC5672 allows multiple configurations. As mentioned earlier, the optimal dynamic performance is generated using the differential output of the converter. This differential output circuit can be composed of RF transformer or differential amplifier configuration. The transformer configuration is the ideal configuration of most applications of AC coupling, and the operational amplifier is suitable for DC coupling configuration.

For applications that require single -pole output voltage, you can consider single -end configuration. Convert a resistor from any output end and convert the output current into a ground reference voltage signal. In order to improve DC linearity by maintaining virtual grounding, I-TO-V or op amp configuration can be considered.

Transformer differential movement

A convenient way to convert the difference output signal into a single -end signal using the radio frequency transformer, while achieving excellent dynamic performance. Select the appropriate transformer carefully according to the output spectrum and impedance requirements.

The advantage of the configuration of differential transformers is to significantly reduce the co -mode signal, Thereby improving dynamic performance within a wider frequency range. In addition, by selecting the appropriate impedance ratio (winding ratio), the transformer can provide the best impedance matching, while controlling the compliance voltage of the converter output.

FIG. 22 and FIG. 23 shows the configuration of the impedance ratio of 1: 1 and 4: 1, respectively. Note that the central tap of the transformer input must be ground to enable DC current. Applying a 20 mAh full-standard output current will cause a 0.5-VPP output of 1: 1 transformer and 1-VPP output of 4: 1 transformer. Generally speaking, the output distortion of the 1: 1 transformer configuration is slightly better, but the output power of the 4: 1 transformer will be 6DB higher.

Single -end configuration

FIG Essence The node IOUT2 u200bu200bmust be connected to the agng, or use the resistor of 25 u0026#8486; to the agng. When the output current of 20 mAh is applied, the rated resistor load of 25 u0026#8486; the differential output motion of 1VPP is generated.

Reference operation

Internal reference

DAC5672 There is a film reference circuit, including the 1.2V band gap benchmark and two controls A amplifier, one DAC. DAC5672's full standard output current iOUTFS is determined by the value of the reference voltage VREF and the resistor RSET. IOUTF can be calculated through the following formulas:

Reference control amplifier work as a V-I converter to generate a reference current IRef. Iref is determined by the ratio of VREF and RSET (see equivalent format 9). The full marked output current IOUTFS is obtained by Iref by a fixed factor 32.

When using internal reference, 2-k u0026#8486; resistance value can generate a full standard output of about 20 mA. Considering a resistor with a tolerance of 1%or higher. Choose a higher value, the output current can be adjusted from 20 mA to 2 mAh. For reasons to reduce total power consumption, improve distortion performance, or observe the output compliance voltage restrictions under the given load conditions, it may be desirable to operate DAC5672 under the output current below 20 mAh.

It is recommended to use 0.1 μF or higher ceramic chip capacitor to bypass Extio pin. Control the internal compensation of the amplifier, and its small signal bandwidth is about 300 kHz.

External reference

You only need to apply an external reference voltage on the EXTIO pin to disable the internal benchmark. In this case, the Extio pins play a role in input. For more accuracy and drift performance or increase dynamic gain controlThe application of capacity can consider using external benchmarks.

Although the 0.1-μF capacitor is recommended to use the internal benchmark, the capacitor is optional for external benchmark operation. Reference Extio has high input impedance (1 m u0026#8486;), which can be easily driven by various power supply. Note that the voltage range of the external benchmark must be kept within the conformity range of the reference input.

gain setting options

Full standard output current on DAC5672 can be set in two ways: set each channel setting in two DAC channels alone, or set up two channels at the same time, set up two channels settings settings Essence For the independent gain setting mode, the GSET pin (pin 42) must be low (that is, connected to Agnd). In this mode, two external resistors need to be connected to the BIASJ U A pin (pin 44), and the other is connected to the BIASJ U B pin (pin 41). In this configuration, users can flexibly set and adjust the full standard output current of each DAC, allowing compensation for the possible gains that may be matched in other places in the transmitting signal path.

Or, make GSET pins high (that is, connect to AVDD), DAC5672 switch to synchronous gain setting mode. At present, the full standard output current of the two DAC channels is determined by only one external RSET resistor connected to the Biasj U A pin. The resistor at the biasj_b pin can be removed; however, this is not necessary, because the pin does not work in this mode, and the resistor has no effect on the gain equation.

Sleep mode

DAC5672 has a power -off function. If there is no clock, you can reduce the total power current to about 3.1 mA within the specified power range. Apply a logical power loss mode on the dormant pins, and the logic is lowered to use the normal operation. When it is not connected, the internal pull -down circuit can make the converter work normally.