Features

Four independent line drives, above 100 mA

to 35 V output

Input signal between -7 V and +35 V [123 ]

Preset threshold

Push pull output, with three -state control and real zero current between VS and land

The current of each output is limited to a complete ground to vs Output voltage range

output voltage clamp to VS and ground

ultra -temperature, under pressure protection

over -temperature, under voltage diagnosis and over current

Preset delay of over -current diagnosis

High -speed operation: up to 300 kHz, 35 v

Placing

l6374

Special design for 24 volt signal levels (IEC 61131, 24VDC).

Overheating protection (OVT)

If the chip temperature exceeds Th (measured at the center of the chip), the chip will cause itself to lose itself. The following measures are taken:

All output levels are forced in the three -state state, that is, the output pins are cut; only the clamp diode on the output end maintains the activation state; the activation signal diagnosis (low activation). Once the chip (usually after a few seconds), the temperature monitored by normal operation is returned to TH-HT. Different upper and lower thresholds have delayed behaviors, ensuring that unrecombinability can generate conditions.

Impolosculent protection (UV)

Even its reference value is considered to be 24 volts. Within this range, L6374 works normally. Below 10.8 V, the entire system must be considered unreliable. Therefore, the power supply voltage is continuously monitored, and a signal called UV is generated and used. As long as the power supply voltage does not reach the internal threshold limit, the signal opens VS comparator (called VSH). Ultraviolet signals disappear above VSH. Once the ultraviolet signal is eliminated, the power supply voltage must be reduced to lower than the threshold before the opening (that is, lower than VSH-HYS1). The lag HYS1 is used to prevent the device from running intermittently at a low power supply at the average value. UV signal inhibit the output, which makes them in three states, but operates the reference voltage for internal comparators, or the operation of the charging pump circuit.

Diagnostic logic

The situation of the DIAG output pin monitoring and sent signal includes: current limit (OVC); 8 separate current limiting circuits, two outputs of each circuit, that is, that is, that is,, that is, Each output transistor is one; they limit the current value of each output at 150 mA, equal to all output currents;

under pressure protection (UV);

[1)23] Excessive protection (OVP); diagnostic signal transmits leakage output by opening path transmission (easy to wired or connected to multiple such signals) and low levels to indicate at least the above -mentioned monitoring.

Programmable latency

Even if there is no actual failure, it can also be required to be required to work in a capacitance if the load is a capacitance load or incandescent lamp (that is, the initial heating phase shows very much in the initial heating phase (the initial heating phase shows very much in the initial heating stage very much. Low resistance). In order to avoid misleading short -diagnostic pulse restriction circuits that are consistent with current intervention, when working under the capacitance load, the or of the current restriction signal is used as a signal path between the external diagnosis. Charging (or discharge) with a 24 V 5NF capacitor requires about 1 μs, and the current is 120 mAh. External capacitors (from a current -limited intervention diagnostic activation circuit from an current restricted intervention diagnostic activation circuit) can be connected to the pinch C3 and grounding (the needle pin C3 is kept open in other circumstances). Then, the capacitance connected to the pin should be used according to the ratio of about 10 pf/μs.

Simulation input (i1, i2, i3, i4)

The input level of each channel is a built -in high -performance comparator (200 MV) high antidity. Each comparator has a input connection to all other pins reference (pin 11). If this pin is the diagram of the internal accurate application band gap (1.25 V), otherwise these inputs can be the internal limit of the external voltage source (from 0 to 5 V) and the current. Another input pin of each comparator can swing from -7 to 35 volts. For this reason, it has implemented the structure and the device shown in Figure 4 as a line receiver. When the input voltage is negative, the current is limited by 15 k the internal limit of the resistor component is shown in Figure 4. High and low input thresholds can pass half of the delayed pins of REF voltage (see page 10 Figure 5).

Status/Push -pull input

Enter 3ST/PP for digital input signals. It has an internal threshold set to 1.26 V; the internal bias circuit (usually 10 mA) simulates high levels (three state), if the pin is broken.

The output stage switch

A cross -transmission of two crystal tube of the output stage of L6374 will be obvious noise, because the transistor here can carry more than more than more 100 mAh, even at the current restricted circuit is really effective. Therefore, the design of the device is to avoid this cross -conductor. When the switch is converted, the transistor is first cut off during conductivity. Then, the interval after the safe is about 200ns, and the other transistor is opened. When analyzing the switching cycle and related switching time, it is necessary to determine some subsequent stages:

delay from the input pins to the output reaction;

[1]23] Output level lost;

Dead area

output level conversion

FIG. 6 helps understand this order. In fact, a pure resistance load is connected to VS/2 non -parasitic interference. The waveform can be significantly reduced and easy to explain. If the load is not completely symmetrical, as shown below. For example, it is enough to connect the resistance load to the ground or VS, as shown in Figure 7 and 8 -to display some switching phases described in the hidden. If the load is grounded, the waveform is in the high impedance state as long as the output of the ground; when the load is connected to VS, the waveform will stay near the power supply voltage as long as possible. If an output load is consolidated by an inductance and a resistor, the inductance will produce a expected effect at the beginning of the transformation of the output

When the inductor can be discharged, the switch will be performed; if The output is the delay switch transition tends to start the charging phase (see Figure 9). With parasitic elements with almost no load, waveforms are similar to waveforms under pure resistance. For real and more complicated loads, the effects of induction and resistance and resistance loads will be more obvious. When a capacitor and resistor are connected as a load, you can see another waveform (as shown in Figure 10). As long as the output level is kept in a transient high impedance state, the output voltage will follow the classic RC relaxation index law. Once another transistor is connected and charged, the waveform will quickly achieve its stable state value. From the above, the switching time can be seen, and the inherent is very fast. If the output load is inaccurate, it is difficult to identify the output level consideration in the waveform. Figure 11 shows the typical switching waveforms input and output.

Application Instructions

It is recommended not to let reference sales (sales 11) Floating: If you do not have an external voltage benchmark, it is best to be in this needle and ground. The capacitor filter output -level direction of reference voltage according to the voltage peak. This is very common when using a capacitance load: In fact, the initial transient of such loads is short -circuit, so the current flowing output is very high nail. In addition, if the device is used as a line receiver. (That is, the input signal can reach the ground) Refinitely requires the REF pin (pin 11) cannot float: In this case, the pin can be connected to the ground or fixed external reference voltage.