-
2022-09-16 16:00:09
CPC7583 is a wire card access switch
Features
Small 28 -pin surface installation SOIC packaging
single -chip integrated circuit reliability
low match matching match Rdson
The need for the zero cross switch to eliminate
flexible switch time, can be converted from a ringtone mode to idle/call mode
#8226; Clean, bouncing switch
Level 3 protection, including integrated current limit, heat shutdown and slIC protection
5V operation, power consumption lt; 10MW
Smart battery monitor
Lock logic level input, no drive circuit
Series
Application
Central Office (CO)
Digital ring road carrier (DLC)
Pbx system
Digital adding main line (DAML)
Hybrid fiber coaxial cable (HFC)
Optical fiber in the ring (ring (ring (ring (ring ( Fitl)
Cheng -paired gain system
Channel Bank
Instructions
Order information
alternate Operation
Note that using TSD as input can also be broken first and then combined. In the second and third lines of Table 10,It is not to use logic input pins to force the full level state, but forced TSD grounding. This will cover the logic input and force the state. Keep this state 25 milliseconds. During the 25 milliseconds in this 25 milliseconds, the input was switched from 10 (bell) to 00 (free/call status). After 25 milliseconds, release the TSD, return the switch to the input pin, and the input pin will set the idle call status.
When using CPC7583 in this mode, forced TSD grounding will cover the input pin and enforce the state of the whole level. Setting TSD to+5V will allow switch control through logical input pins. However, setting TSD to+5V will also disable the heat shutdown mechanism. It is not recommended to do this. Therefore, in order to allow the switch control through logical input pins, TSD is allowed to float.
Therefore, when using TSD as the input, the proposed two states are 0 (covering logic input pins and forced all closure status) and floating (allowed to control the switch by logical input pins, and the heat is turned off. The mechanism is active). This may require the use of road collector buffer.
1. If TSD 5V, the heat shutdown mechanism is disabled. If TSD is floating, the heat shutdown mechanism is activated.
2. Forced TSD grounding will cover the logical input pin and enforce the state of the full level.
3. Status/call status.
4. Test status.
5. Test status.
6. Power ringtone status.
7. Test status of the bell generator.
8. Test and test status at the same time.
9. Full Customs Status
Input/parallel output data locks in parallel input/parallel output data are integrated in CPC7583. The operation of the data lock is controlled by a logic -level input pin lock. The data input of the lock memory is the input tube of the CPC7583. The output of the data lock is used for internal nodes for state control.
When the locking control pin is located at Logic 0, the data locks are transparent, the data control signal is directly flowing from the input, and the data locks flow to the state control. Any change in input will be reflected in the state of the switch.
When the lock control pin is located at Logic 1, the data locks are activated; CPC7583 will no longer respond to the change of the input control pin. The state of the switch is now locking; that is, when the lock input is converted from logic 0 to logic 1, the state of the switch will remain unchanged. As long as the lock is kept at a high position, the switch will not respond to the change of input.
Please note that the TSD input is not bound to the data lock. TSD is not affected by the input of the lock. TSD input will be controlled by input and locking.
1. If TSD 5V, the heat shutdown mechanism is disabled. If TSD is floating, the heat shutdown mechanism is activated.
2. Forced TSD grounding will cover the logical input pin and enforce the state of the full level.
3. Status/call status.
4. Test status.
5. Test status.
6. Power ringtone status.
7. Test status of the bell generator.
8. Test and test status at the same time.
9. Status in full level
10. Synchronous test output ring test status.
Parallel input/parallel output data locks are integrated in CPC7583. The operation of the data lock is controlled by a logic -level input pin lock. The data input of the lock memory is the input tube of the CPC7583. The output of the data lock is used for internal nodes for state control.
When the locking control pin is located at Logic 0, the data locks are transparent, the data control signal is directly flowing from the input, and the data locks flow to the state control. Any change in input will be reflected in the state of the switch.
When the lock control pin is located at Logic 1, the data locks are activated; CPC7583 will no longer respond to the change of the input control pin. The state of the switch is now locking; that is, when the lock input is converted from logic 0 to logic 1, the state of the switch will remain unchanged. As long as the lock is kept at a high position, the switch will not respond to the change of input.
Please note that the TSD input is not bound to the data lock. TSD is not affected by the input of the lock. TSD input will be controlled by input and locking.
Function description
Introduction
CPC7583 has eight different states. Please refer to the true value tables in Table 12 and 13 to understand the differences in version.
free/call status (disconnect switch SW1 and SW2 closed). All other switches are turned on.
belling state (the bell switch SW3, SW4 is closed). All other switches are turned on.
ring access (ring access switch SW5, SW6 closed). All other switches are turned on.
ring generator test status (SW7, SW8 closed). All other switches are turned on.
SLIC test status test switch (SW9, SW10).
synchronous cycle and slice access status. (SW9, SW10, SW5 and SW6 are closed). All other switches are turned on.
Synchronous test output and ring circuit test (SW5, SW6, SW7, SW8 closed). All other switches on the BC ABD BD version are opened.
full level status (all switches are turned on).
CPC7583 provides a breakdown, then combined and then disconnected switch through simple logical level input control. The solid switch structure means that pulse noise will not produce during switching during the ring frequency or ring check, so there is no need to over -zero switch circuit. Status control is input through logic levels, so there is no additional driving circuit. The disconnected switch SW1 and SW2 are linear switches, which have unusually low RDSON and excellent matching features. The breakdown voltage of the bell access switch SW4 GT; 480V, has sufficient breakdown voltage and proper protection to prevent breakdown when a transient failure occurs. (That is, transmit transient to the ring generator).
CPC7583 integrates the diode bridge clamp circuit, current limit and heat clearance mechanism, providing protection for SLIC devices under failure. Positive and negative waves are reduced through the current limiting circuit and controlled to the ground power level through the diode. Power cross transients are also reduced by current restrictions and heat shutdown circuits.
In order to protect the CPC7583 from being affected by pressure failures, auxiliary protectors need to be used. The secondary protector must limit the voltage at the tip and ring terminal to the level below the maximum breakdown voltage of the switch. In order to minimize the stress on the solid -state contact, it is recommended to use a folding or pry rod -type secondary protector. After the correct selection of the secondary protector, using the CPC7583 line card will meet all related ITU, LSSGR, FCC or UL protection requirements.
CPC7583 works only through+5V power. This makes the device have extremely low idle and active power consumption, and allows the use of almost any range of battery voltage. CP7583 also uses battery voltage as a reference for integrated protection circuit. In the case of battery voltage loss, CPC7583 will enter the full level state.
Switching time
CPC7583 When switching from bell -stimulating to idle/call state, it can use simple logic level input Switch SW1 and SW2 Status release time. This is called first -in -one, then disconnection or break first and then operation. When the line disconnect switch contacts (SW1, SW2) are closed (or closed) before the ring connection switch contact (SW3, SW4) is disconnected (or disconnected), this is called the first -in -one and then disconnection operation. Before the lines of the line disconnect switch (SW1, SW2) are closed (closed), when the bell access contact (SW3, SW4) is disconnected (disconnected), it occurs first and then combined. Using CPC7583, by applying logic levels to the input end, input and input terminals of the device, you can easily select And break first and then operation.
Table 9 and Table 10 gives the logical order of two operation modes. Table 12 and 13 gives logical state and explanation.
Using pin 13 (TSD) as the input, you can also implement it first and then combined. In Table 10, in the second and third lines of Table 10, you can induce the switch by applying a logical input to the pins instead of applying a logical input to the pin. Full Customs . This has the effect of covering logic input and compulsory equipment into the full level state. Keep this input state during the maintenance period during this maintenance period, switch the input from the bell state to the free/call state. After 25ms, 25ms. , Release the pin 13 (TSD), return the switch to the input of Intestout, Inring, Intestin, and reset the device to the IDLE/TALK state.
Set the pin 13 (TSD) to+5V will Allows the use of logic input for switch control. However, this setting will also disable the heat shutdown circuit, so it will not be recommended. When should input pins (13) input and input when it is allowed. When controlling, the two states are 0, which will force the device to enter the full level or allow logic input to remain unchanged. ] Circular access switch Zero cross -current offset off
After the application logic input is turned off, the ring access switch is designed to be designed to change Therefore, it is not used in switching pure DC signals. No matter what logical input, the switch will be kept in the connection state until the next time it is over zero. These switching characteristics will be reduced and may eliminate the entire system pulse related to the ringling switch. Noise. The characteristics of the bell connection switch make the zero -cross switching scheme possible. The minimum impedance of the proposal to connect with the ring generator is 300 #8486;.
Power supply+5V power supply The voltage and battery voltage are connected to CPC7583.CPC7583 switch state control is only powered by+5V power supply. Therefore, CPC7583 shows extremely low power consumption in activity and idle state.
battery voltage monitor
CPC7583 also uses reference voltage to monitor the battery voltage. If the battery voltage is lost, the CPC7583 will immediately enter the full level state and maintain this state until the battery voltage is restored. If the battery voltage rises above -10V, the equipment will also be Enter the full level state until the battery voltage drops below -15V. This battery monitor function will absorb a small amount of current ( lt; 1 μA) from the battery, and will slightly increase the overall power consumption of the device.
Protection
Diode Bridge/SCR
CPThe C7583 combines a combination of restricted road switch, diode bridge/SCR clamp circuit and thermal offer to protect the derivative of SLIC devices or other related circuits during the stomach (such as lightning). Under normal transient conditions, fault currents pass through the diode bridge to ground. During the negative transient period of 2 volts or 4 volts higher than the battery negative voltage, thyristor is performed, and the faults are diverted to the ground through the thyristor and diode bridge.
In addition, in order to make SCR open or fold, the connection voltage of SCR (see Table 11) must be less than the negative value of the battery reference voltage. If the battery voltage is lower than the negative voltage of the SCR connection voltage, the SCR will not pry open, but it will guide the fault current to the ground.
For the power sensing or the cross -failure fault of the power supply, the positive cycle of the transient state was cut to the diode to fall to the ground, and the fault current was directed to ground. When the voltage exceeds the battery reference voltage of 2 to 4 volts, the negative cycle of the transient will cause SCR to turn on, thereby turning the current to ground.
Flow limit function
If lightning attack transient when the device is in a call/idle state, the current will be transmitted along the line to the comprehensive protection circuit, and the dynamic limits of SW1 and SW2 are subject to disconnect switch SW1 and SW2 Restrictions on flow response. When 1000V 10x1000 pulse (LSSGR lightning) is applied to the line through appropriate clamping external protectors, the current seen at the pin 6 (TBAT) and pin 23 (RBAT) will be a typical amplitude and persistence. The pulse of 2.5A and lt; 0.5ms.
If the power supply occurs in a cross -call/idle state, the current passs through the disconnect switch SW1 and SW2 into the integrated protection circuit, and it is limited by the dynamic DC current restrictions of the dynamic DC current of the two disconnect switches. The specified over -temperature DC current limit is between 80mA and 400mA, and the circuit has negative temperature coefficients. Therefore, if the device is heated due to the cross -failure failure of the power supply, the measurement current at the pin 6 (TBAT) and the pin 23 (RBAT) will be reduced as the equipment temperature increases. If the temperature of the device is high enough, the temperature closing mechanism will be activated, and the device will be default to the full level state.
Temperature shutdown
When the equipment temperature reaches a minimum of 110 #978; In this heat shutdown mode, the number of pins 13 (TSD) is 0V. The normal output of TSD is+VDD.
If a short -term transient state (such as lightning events) occurs, the heat clearance function is usually not activated. However, in an extended power cross transient, the equipment temperature will rise, and the heat shutdown will be activated, forcing the switch to enter the full level state. At this time, the current at the pin 6 (TBAT) and the pin 23 (RBAT) will be reduced to zero. Once the device enters the heat shutdown state, it will maintain the full level stateUntil the temperature of the device drops below the activation level of the heat clearance circuit. This will restore the device to the state before the heat shutdown. If the transients are not passed, the current will limit the value flow allowed by the dynamic DC current of the switch and start heating again to re -activate the thermal shutdown mechanism. As long as the failure still exists, the cycle of entering and exiting the heat shutdown mode will continue. If the severity of the failure is large enough, the external secondary protector can activate and divert all currents to the ground.
By applying+VDD on the pin 13 (TSD), the thermal check mechanism of the CPC7583 can be disabled.
External protection element
CPC7583 only needs to set up a overvoltage secondary protector on the side of the device loop. The above comprehensive protection characteristics eliminate the need for line protection. The role of the secondary protector is to limit the voltage to the level of breakdown voltage or input output isolation grid without exceeding the CPC7583. It is recommended to use a folding or crowbar type protector to minimize the stress on the device.
Formulas about the specifications of external secondary protectors, fuse resistors and PTC specifications, please refer to the application description of Claire's application instructions AN-100.
Data lock memory
CPC7583 has an integrated data lock.辑 Lock operation is controlled by the logic level input pin 18 (闩 lock). The data input of 设 lock is the internal node of the device's scoot 15, insert 16 (Inring), and insert 17 (Intestin). When the lock control pin is located on logic 0, the data lock is transparent, and the data control signal is directly controlled through the state. The changes in input will be reflected in the change of the switch state. When the 闩 lock control pin is located in logic 1, the data locks are now in a state of activity, and the changes in the input control will not affect the switch state. When the locks change from logic 0 to logic 1, the switch will be kept in the original position. As long as the locks are in Logic 1, the switch will not respond to the change of input. In addition, TSD input is not binding with data locks. Therefore, TSD is not affected by the input of 输 locks. TSD input will cover the status control by inserting scoot 15, insert 16 (Inring), and pink 17 (INTESTIN) and 闩 locks.
Mechanical size