The IC voltage of the working power supply is 5V

to 12V The bus

up to 1.3A grid current capacity

TTL compatible 5 -bit programming [123 ]

The output conforms to VRM 9.0: 1.100V to 1.850V, binary 0.025V

voltage mode PWM control

High output accuracy: ± 1%overline and temperature ] Change

Quick load transient response: from 0%to 100%duty occupation ratio

The power supply is good output voltage

Overwharration protection and

Surveillance monitoring Instrument

Realize overcurrent protection

Use MOSFET's RDSON

200kHz internal oscillator

External adjustable oscillator

from from the way 50kHz to 1MHz

Soft start and inhibitory function

Advanced power supply

Core microprocessor

distributed power supply

]

Ultra-power DC-DC regulator

Instructions

This device is a power controller, which is specially designed to provide high-performance DC/DC with high-performance DC/DC for large current microprocessors Convert. The accurate 5 -digit modular converter (DAC) allows adjustment of the output voltage from 1.

30V

to 2.05V, 50mv two -way advance, from 2.10V to 3.50V, and 100MV can move in. High -precision internal bases ensure that the selected output voltage is within ± 1%. The current door -driven door of the peak provides an external power MOS that provides a low -opening loss loss. The device guarantees the rapid protection of the current and overvoltage of the load. The external SCR triggers the overvoltage of the input power when the failure occurs. As long as the internal crowbar is also provided to the low -side MOSFET as long as the voltage is detected. If the current is detected, the soft startup capacitor discharge, and the system works in snoring mode.

Electrical characteristics (VCC 12V, ambient temperature 25 ° C, unless there are other regulations)

[ 123]

Device description

This device is an integrated circuit implemented by BCD technology. It provides a complete control logic and protection optimizing microprocessor power supply for high-performance antihypertensive DC-DC converters. It is designed to drive N -channel MOSFET in the synchronous rectification buck topology. This device works normally, the VCC range starts from 5V to 12V, and starts from 1.26V power -level power supply voltage (VIN)The output voltage. The output voltage of this converter can be accurately adjusted, programmable VID pins, from 1.100V to 1.850V, using 25mV two to advance, and the maximum tolerance of temperature and wire voltage changes is ± 1%. This device provides a voltage mode control of fast transient response. It includes a 200kHz self -excitement oscillator from 50kHz to 1MHz. The error release large has a 15MHz gain bandwidth and 10V/μs conversion rate, which allows high conversion bandwidth to achieve fast transient performance. The generated PWM duty ratio is 0%to 100%. The device prevents over -current from entering the card stagnation mode. The device eliminates the need for current sensitive resistance by using the upper MOSFET RDS (on). The device provides SO20 packaging

oscillator

The switching frequency is fixed to 200kHz internally. The internal oscillator produces triangular waveforms to PWM charging and discharge and constant current capacitors. The current is usually 50 μA (FSW 200kHz), which can be connected to the RT pin and GND or VCC. Because the RT pin is maintained at a fixed voltage (typical. 1.235V), the frequency variable is a current that is sink (voltage) in proportionally from the flow. In particular, the frequency connected to the GND increase (current from the pins), according to the following relationship:

When connecting the RT to VCC 12V or VCC 5V Reduce (the current is forced into the pins), according to the relationship with the following:

The relationship between the switching frequency and the RT is shown in Figure 1. Please note that when the pin is applied to this pin, there is no current to pass to an oscillator because there is no current.

digital mode converter

The built -in digital mode converter allows the output voltage from 1.30V to 2.05V50MV. V, 100mv two move forward, as shown in the previous table 1. This fine -tuned the internal benchmark to ensure 1%accuracy. The adjustment internal reference voltage is programmed by voltage recognition (VID) pin. These are the internal DAC TTL compatible inputs, which are implemented by providing an internal reference voltage. VID code drives multi -road reusopter, the multi -road repeat device is at the point of the separation line. The DAC output is transmitted to the amplifier that obtains the Vprog reference voltage (that is, the setting value of the error amplifier). Provide internal pulling (achieved through a 5μA current generator); in this case, the programming logic 1 is enough to let the pins float, and the programming logic 0 is short enough to pins. Voltage recognition (VID) pin configuration also sets good power threshold (PGOOD) and overvoltage protection (OVP) threshold. The VID code 11111 disables the device (as a short circuit on the SS pin) and does not regulate the output voltage.

Soft start and inhibitory

When starting, charged to the external capacitor CSS through the 10 μA constant current to generate a slope, as shown in Figure 1. When the voltage on the soft startup capacitor (VSS) reaches 0.5V, the low -power MOS is turned on to the DIS to charge the output capacitor. When the VSS reaches 1V (the lower limit of the oscillator triangle wave), the upper limit MOS starts the switch and the output voltage begins to increase. The VSS growth voltage initially cut the output of the error amplifier, so VOUT linear increased, as shown in Figure 2. At this stage, the system works in a loop. When VSS is equal to VCOMP, release the clamp of the error amplifier output end. In any case, another clamping of an error amplifier input is kept activated, allowing VOUT to increase at a lower slope (ie, the slope of the VSS voltage, see Figure 2). In the second stage, the system works in a closed loop, and the reference value continues to increase. When the output voltage reaches the required value Vprog, and the clamping on the input of an error amplifier is removed and the soft start is completed. The maximum value of VSS is about 4V. If the VCC and OCSET pins exist at the same time, the soft start will not occur, and the internal short circuit inside the related pin does not exceed its starting threshold. During the normal operation period, if one of the two power supply is short -circuited to the GND inside the SS pin, the SS capacitor is quickly discharged. The device enters the state of suppression, forcing the SS pin to be less than 0.4V. In this case, the two external MOSFETs remain unchanged.

The driver capacity of the driver's room height and low -voltage drive allows the use of different types of power MOS (can also reduce RDSON) to keep fast switch conversion. The low -voltage side MOS driver is directly provided by VCC, and the high -voltage side drive is provided by the starting pin. Using adaptive dead zone control to prevent cross -conductors and allow multiple types of MOS FETs. When the grille is greater than 200mv, the upper MOS is avoided, and the lower MOS is turned on to avoid if the phase pins exceed 500 millivolta, it should be avoided. In any case, the upper MOS is closed on the low pressure side. At 5V and 12V, the peak currents of the upper (Figure 3) and the bottom (Figure 4) are used in these measurements of 4NF capacitors. For lower drivers, the source peak current is 1.1a@vcc 12v and 500ma@vcc 5V, while the Sink peak value is 1.3A@vcc 12V, 500ma@vcc 5V. Similarly, for the upper -layer driver, the source peak current is 1.3a@vboot vphase 12V and 600ma@vboot vphase 5V, and the peak of the trap is 1.3a@vboot vphase 12V and 550ma@vboot vphase 5V.

Monitoring and protection

output voltage passes throughPin 1 (VSEN) monitor. If the value of the ± 12%(typical value) of the programming value is not valuable, the PowerGood output is forced to be low. When the output voltage reaches one nominal. If the output voltage exceeds this threshold, the OVP pin will be forced to high level, which will trigger the external SCR off the power (VIN). As long as the voltage is detected, the lower drive will be turned on. In order to perform current protection, the device compares the voltage drop of the high -voltage side MOS because the voltage of the external resistance (ROCS) is connected to Moss between the OCSET pin and the drain. Therefore, over -current threshold (IP) can be calculated through the following relationship:

When the typical value of IOCS is 200 μA. To calculate the ROCS value, it must be regarded as the maximum value of RDSON (also changes with temperature) and the minimum value of Iocs. In order to avoid accidental trigger current protection, this relationship must be satisfied:

Type u0026#8710; i is an inductive ripple current, and iOUTMAX is the maximum output current. In the case of short -circuited output, the soft startup capacitor discharges with constant current (typical value of 10 μA), and the SS pin reaches the 0.5V soft start phase. During the soft startup process, overcurrent protection is always in a state of activity. If such incidents occur, the device will turn off two MOSFETs, and the SS capacitor will be powered off again (after reaching the upper limit of about 4V). The system now works under the snoring mode, as shown in Figure 5A, after excluding the reasons for overcurrent, the device re -operates the power switch normally.

The inductor design

The inductor value is defined by the discount between the transient response time, efficiency and cost. The inductor must be calculated to maintain the output and maintain the input voltage change ripple current u0026#8710; IL between 20%and 30%of the maximum output current. The inductance value can be calculated through the following relationship:

Among them, the FSW is the switch frequency, VIN is the input voltage, and VOUT is the output voltage. Figure 5B shows the ratio of the output voltage of different electrical induction values u200bu200bwhen VIN 5V and Vin 12V. Increasing the electrical value will reduce the ripple current, but it will also reduce the transient response time of the converter load. If the compensation network design is good, the device can open or close the duty ratio up to 100%or drop to 0%. The response time is now the time required to change its current value from the initial value to the final value. Since the inductor has not completed the charging time, the output current is provided by the output capacitor. The shorter the response time, the smaller the output capacitance. The response time of the load transient state is different due to the application or removal of the load: if the load is applied, the inductor is equivalent to the voltage charging voltage between the input and output. During the disassembly process, it only discharge from the output voltage. The following expression gives the compensation network ringIn the case of fast enough u0026#8710; I to load the approximate response time:

The worst case depends on the available input voltage and selected output voltage Essence In any case, the worst case is the response time after the load removal, the minimum output voltage is programmed, and the maximum input voltage is available.

Output capacitor

Since the microprocessor requires a current change of more than 10A when the microprocessor is undergoing a load, the output capacitor is the basic component of the rapid response of the power supply. In fact, in the first few micro seconds, they provide current to the load. The controller immediately identifies the load transient and sets the duty cycle to 100%, but the current slope is limited by the inductor value. Due to the current changes in the capacitor (ignore English)

During the load transient state, a minimum capacitor value is required to maintain the current without discharge. The voltage caused by the discharge of this output capacitor can be concluded through the following formulas:

Among them, DMAX is the maximum duty cycle, that is, 100%. The lower the ESR, the lower the output. The lower the static ripple of the output voltage during the transient transient.

Input a capacitor

Input capacitors must withstand the ripple current generated during the upper MOS drive, so it must have a low ESR to minimize the loss. The RMS value of this ripple is:

Among them, D is the duty ratio. When D 0.5, the equation reaches the maximum value. The losses in the worst case are:

compensation network design

The control loop is a voltage mode (Figure 7). It uses the speed reduction function to use the speed reduction function. Meeting the requirements of VRM's requirements, reducing the size and cost of the output capacitor. This method restores the part of the voltage drop caused by the output capacitor ESR in the load transient, and the dependence of the output voltage to the load current is introduced: under the light load, the output voltage will be higher than the nominal level, and at high loads at high loads, at high loads Below, the output voltage will be lower than the nominal value.

As shown in Figure 6, the ESR drops in any case, but the use of the speed reduction function will have the smallest output voltage. In fact, the speed reduction function introduces a static error that is proportional to the output current (VDROOP in Figure 6). Because there is no sensor resistance, the inherent resistance of the inductance is used (several M u0026#8486;). Therefore, the low -pass filtering inductance voltage (ie, the inductance current) is added to the feedback signal to achieve a drooping function in a simple way.指的是如图7所示，闭环系统的静态特性为：

式中，VPROG是数模转换器的输出电压（即设定值）， RL is an inductive resistance. The second item of the equation allows in zero load (u0026#8710; v+) generate positive offset; the third item introduces the drooping effect (u0026#8710; VDROOP). Note that if the following situation occurs, the drooping effect is equal to ESR drop:

Considering the previous relationship, you can determine R2, R3, R8 and R9 As follows: Select a value within the range of hundreds of K u0026#8486; to obtain another actual value component.

According to the above equal form, it is obtained:

Among them, the IMAX is the maximum output current.

It must be selected to obtain R3 u0026 LT; u0026 LT; R8 // R9 to allow these and continuous simplification. Therefore, under the speed reduction function, the output voltage decreases as the load current increases, so DC output impedance is equal to the resistance path. When the output impedance and frequency are constant, it is easy to verify that the output voltage deviation of the load transmission is minimal. In order to choose other components of the compensation network, the transmission function of the voltage ring was considered. In order to simplify the analysis, assuming R3 u0026 LT; u0026 LT; RD, where RD (R8 // R9).

You can ignore the connection between the R8 and phase to calculate the transmission function, because as it will be seen later, this connection is only important at low frequency. So R4 is considered to be related to VOUT. With this consumption, the voltage circuit has the following transmission functions:

Note: In order to understand the reason for the previous assumptions, the scheme in Figure 9 must be considered. In this scheme, because the electromot current is instead of the drooping function within the frequency range, these currents are basically the same for the drooping function, and it is assumed that the drooping network does not represent the electrical sensor charging.

Because of the scope of interest | Gloop | u0026 gt; u0026 gt; 1. In order to get a flat shape, the considering relationship will naturally follow. Application ideas: 1.100V to 1.850V/25A Figure 10 shows a schematic diagram of 1.100V to 1.850V conversion with a current capacity of 25A. Because the device uses high grid pole driver, MOSFET on high, low -voltage side can use STS11NF30L (30V, 9MW typical value@vgs 10V) MOSFET with more than three high -voltage sides. It is also recommended to use four MOSFETs as low -voltage side switches.