Features

Support 20 MHz to 85 MHz displacement clock

85 mHz RX power consumption lt; 142 mw (typical value)

RX power off mode lt; 1.44 mW (maximum) ESD rated value gt (HBM), gt; 700 v (eiaj)

#8226; Support VGA, SVGA, XGA, and single pixel SXGA

PLL does not require external components

compatible with TIA/EIA-644 LVDS standard

123] Lightly 56 -needle or 48 -pin TSSOP package

DS90CF386 also provided 64 -pin 0.8 mm thin spacing grid (NFBGA) packaging

Application

Video display

Printer and images

Digital video transmission

# 8226; Machine vision

Open the Local Design Institute to the RGB Bridge

Instructions

DS90CF386 receiver to turn four LVDS (low -voltage differential signal) data flow transition back to return back to return back to the return back to the return return back to the return return back to the return return back to the return return back to the return back to the conversion back to return back to the return return back to the return return back to the conversion back to return back to the return back to the conversion. Parallel 28 -bit LVCMOS data.

DS90CF366

The receiver is also available, and it converts three LVDS data back to parallel 21 -bit LVCMOS data. The output of the two receivers is selected on the bottom of the decline. The rising or decline along the selection transmitter will be operated with the decline along the selection receiver, without any conversion logic. The receiver LVDS clock works at a rate of 20 MI to 85 MM. The equipment phase is locked to the input LVDS clock, sampled serial flow on the LVDS data cable, and converts it to parallel output data. At the input clock rate of 85 MHz, each LVDS input cable runs at the 595 Mbps bit rate, so the maximum throughput of DS90CF386 is 2.38 Gbps, and the maximum throughput of DS90CF366 is 1.785 GBPS.

The use of these serial link devices is an ideal choice to solve the problem of EMI and cable size. These problems transmit the LVCMOS interface with wide and high -speed parallel data. Both devices are packed in TSSOP. DS90CF386 also offers a 64 -pin 0.8 mm thin spacing grid array (NFBGA) packaging. Compared with 56 -pin TSSOP packaging, the package can reduce the PCB area of 44%area.

Equipment information

(1), please refer to the appointment appendix at the end of the data table.

Typical application frame diagram (DS90CF366)

Sequence diagram

(1 ) In the worst case, the test mode will generate the maximum switching of digital circuit, LVDS I/O and CMOS or LVCMOS I/O. (2), 16 grayscale test mode testing the equipment power consumption of typical LCD display mode. The test mode is similar to the signal switching required for a set of 16 vertical stripes on the display.

(3), Figure 1, and Figure 3 showed the decrease in data selection (TXCLK IN/RXCLK OUT).

(4), the recommended needle to the signal mapping. Customers can choose different definitions.

(1) The test mode in the worst case will generate the maximum switching of digital circuit, LVDS I/O and CMOS or LVCMOS I/O.

(2), 16 grayscale test mode testing the equipment power consumption of typical LCD display mode. The test mode is similar to the signal switching required for a set of 16 vertical stripes on the display.

(3), Figure 1, and Figure 3 showed the decrease in data selection (TXCLK IN/RXCLK OUT).

(4), the recommended needle to the signal mapping. Customers can choose different definitions.

C: Settings and maintenance time (internal data sampling window) by RSPOS (receiver Input selection position) The minimum and maximum value definition TPPOS: the output pulse position of the transmitter (minimum and maximum) Cable crooked: usually 10 PS – 40 PS per feet, depending on it depends on it Medium

RSKM cable tilt (type, length)+source clock jitter (cycle to cycle) (1)+ISI (interference interference between symbols) (2)

[1) The cycle jitter depends on the delivery source. The clock shake should be less than 250ps at 85MHz.

(2), ISI depends on the length of the interconnection; it may be zero.

Typical features

Detailed description

Overview

DS90CF386 is a receiver, it will four LVDS ( Low -voltage differenceSignal) Data flow to 28 -bit LVCMOS data (24 -bit of RGB and 4 digits of Hsync, Vsync, DE, and CNTL). This DS90CF366 is a receiver that converts three LVDS data into parallel 21 -bit LVCMOS data (18 -bit RGB and 3 -bit Hsync, VSYNC, and de). A LVDS clock range locked to the input LVDS clock range from 20 to 85 MM. The lock -up loop ensure a stable clock in order to sample the output LVCMOS data on the top of the receiver clock output. These devices have a PWR DWN pin. When input data without activity, the device is placed in a low -power mode.

Function box diagram

Feature description

DS90CF386 and DS90CF366 consisting of several key blocks:

LVDS receiver

Locking loop serial LVDS to parallel LVCMOS converter

#8226 ; LVCMOS driver

LVDS receiver

DS90CF386 has five different mobility LVDS inputs, DS90CF366 has four different mobilization LVDS inputs. For DS90CF386, the four LVDS inputs include serialized data from 28 -bit source transmitters.

For DS90CF366, three LVDS inputs include serialized data from 21 -bit source transmitters. The remaining LVDS input contains the LVDS clock that is related to the data.

LVDS input terminal connection

DS90CF386 and DS90CF366 require a 100Ω terminal resistor on the real line and complement lines of each differential pair in the receiver. To prevent reflexes caused by short -term, the resistance should be as close to the device input pin as much as possible. Figure 20 shows an example.

Lock phase loop (PLL)

FPD Link I device uses internal PLL to restore the clock transmitted through the LVDS interface. The recovery clock is then used as a reference to determine the sampling position of the seven string positions received per clock cycle. The width of each bit in the serialized LVDS data stream is one -seventh of the clock cycle. Differential deviations (one differential pair ΔT), interconnection deviation (one differential pair with another differential pair) and clock jitter will reduce the available window of LVDS serial data. Each VCC has a minimum transmitting to the noise of PLL, so as to create a low jitter LVDS clock to improveOverall jitter budget.

Serial LVDS to parallel LVCMOS converter

After locking the input LVDS clock, the receiver turns each LVDS differential data to the back serial sequence to each clock cycle per clock cycle Seven parallel LVCMOS data output. For DS90CF386, LVDS data input is mapped to LVCMOS output, as shown in Figure 8. For DS90CF366, according to Figure 9, LVDS data input is mapped to LVCMOS output.

LVCMOS driver

LVCMOS output from DS90CF386 and DS90CF366 is a back -serial single -end data from serial LVDS differential data pairs. Each LVCMOS output is clock controlled by a drop of frequency from PLL and RxClkout. All unused DS90CF386 and DS90CF366 RXOUT outputs can be kept floating.

Equipment function mode

Power order and power -off mode

This DS90CF386 and DS90CF366 can enter the power -off mode at any time by asserting the PWR DWN pin (low level valid). DS90CF386 and DS90CF366 are also designed to prevent the transmitter from accidentally disconnecting the transmitter or receiving machine. If the transmitting board is powered off, the receiver clock (input and output) stops. Data output (rxout) keeps the clock when the clock stops. When the receiver is broken, the receiver input is controlled by the faulty protection bias circuit. Under the initial power -powered and power -off conditions, the LVDS input is high Z. Each input current is limited to 5 mAh, so as to avoid the possibility of locking when supplying the device.

Application and implementation

Note

The information in the following application chapters is not part of the TI component specification, TI does not guarantee its accuracy or integrity. TI's customers are responsible for determining the applicability of the component. Customers should verify and test their design implementation to confirm the system function.

Application information

DS90F386 and DS90CF366 are designed for multiple data transmission applications. In these applications, the use of serial LVDS data cable allows effective signal transmission on the narrow bus width to reduce costs, power and space.

Typical applications

FIG. 21 and 22 display DS90CF386 and DS90CF366 as typical applications from OpenLDI to RGB bridges.

Design requirements

For this design example, please follow the requirements in Table 1.

Detailed design program [12]3] To design with DS90CF386 or DS90CF366, please determine the following:

cable interface

bit resolution and operating frequency

Bit mapping from the receiver to the end -point panel

interoperability of the pulse position of the transmitter

cable

Launch The cable interface between the machine and the receiver needs to support the differential LVDS pair. DS90CF366 requires four pairs of signal lines, DS90CF386 requires five pairs of signal cables. The ideal cable interface has a constant 100Ω differential impedance on the entire path. It is also recommended to keep the cable below 120ps (assuming the 85MHz clock rate) to maintain sufficient data sampling window at the receiver.

According to different applications and data rates, the interconnect medium between TX and RX may be different. For example, for lower data rate (clock rate) and short cable length ( lt; 2m), the electrical performance of the medium is not so important. For high -speed or long -distance applications, the performance of the medium has become more important. Some cable structures provide closer oblique sex (matching the length between the wire and the wire pair). For example, the distance between dual -coaxial cables is 5 meters, and the maximum data transmission rate is 2.38 Gbps (DS90CF366) and 1.785 Gbps (DS90CF386).

Bit resolution and operating frequency compatibility

The bit resolution of the end -point panel display display DS90CF386 or DS90CF366 is sufficient to output the data required for each pixel. DS90CF386 has 28 parallel LVCMOS output, so it can provide a bit resolution of up to 24 BPP (bit/pixels). In each clock cycle, the remaining positions are three control signals (Hsync, vsync, de) and a spare position. DS90CF366 has 21 parallel LVCMOS output, so it can provide a bit resolution of up to 18 BPP (bit/pixels). In each clock cycle, the remaining positions are three control signals (Hsync, vsync, de).

The refresh rate of the pixels and endpoint panels of each frame indicate the operating frequency required for the rotor clock. To determine the required clock frequency, please refer to Formula 1.

f_clk [h_active + h_blank] × [v_active + v_blank] × f_vertical

h_active Activity display horizontal line

#8226; h_blank Calling WeekPeriod horizontal line

v_active Event display vertical lines

v_blank Vertical line vertical line of the hidden cycle

f_vertical refresh rate (refresh rate ( Hz)

F_CLK LVDS clock working frequency

In each frame, there is a level line that is not actively displayed on the panel. Conditioning cycle. These hidden cycle pixels must be included to determine the required clock frequency. Consider the following examples to determine the required LVDS clock frequency:

h_active 640

h_blank 40

v_active 480

v_blank 41

f_vertical 59.95 Hz

Therefore, the required working frequency is determined by equations 2.

[640 + 40] × [480 + 41] × 59.95 21239086 Hz ≈ 21.24 MHz

The operating frequency of PLL in DS90CF386 and DS90CF366 is between 20 and 85 MHz, so DS90CF386 And DS90CF366 can support panel display with the above requirements.

If the specific elimination interval is unknown, the pixel number in the hidden interval can be approximately 20%of the active pixels. Formula 3 can be used as a conservative value of working LVDS clock frequency: F_CLK ≈ H_Active × V_Active × F_Vertical × 1.2

Use this approximate value. The working frequency of the example in this section is estimated with Formula 4.

640 × 480 × 59.95 × 1.2 22099968 Hz ≈ 22.10 MHz

The data mapping between the receiver and the end -point panel display

ensure that the output of LVCMOS is mapped as an anti -countermeasure The endpoint after serialization shows the RGB mapping requirements alignment. For two common mapping topology of 8 -bit RGB data, see the following.

1.lsb mapped to RXIN3 ±.

2.msb mapped to RXIN3 ±.

Table 2 and Table 3 describes how to map these two popular topology to the DS90CF386 output.

If DS90CF386 or DS90CF366 is used to support 18 BPP, it is usually used Table 2, where RXIN3 ± (if applicable) is retained as ""no connection"". Through this mapping, the MSB of RGB data is retained on RXIN0 ±, RXIN1 ±, and RXIN2 ±, while the two LSB of the original 8 -bit RGB resolution ignore it from RXIN3 ±.

RSKM interoperability

One of the most important factors when designing the receiver into a system application is to evaluate how many RSKM (receiving machine tilted tadpoles) available. In each LVDS clock cycle, the LVDS data stream carries 7 serialized data bit. Ideally, the transmission pulse position of each bit will appear once every (n × t)/7 seconds, where the position position of the n LVDS clock. Similarly, Ideally, the RX selection position of each bit will occur once every ((n+0.5) × t)/7 seconds. However, in the actual system, due to the effects of cable tilt, clock jitter, and ISI, each of LVDS TX and RX will have non -ideal pulse and selection positions. This concept is shown in Figure 23.

In order to determine the absolute minimum value of the entire LVDS position, all left and right spacing of 0-6 must be considered. This absolute minimum value corresponds to RSKM.

In order to improve the RSKM performance between the LVDS transmitter and the receiver, designers usually advance or delay the LVDS clock from LVDS data. Compared with the LVDS data mobile LVDS clock, the setting and maintenance time of the transmitter can be improved, rather than the setting and maintenance time of the receiver.

If the left border is less than the right border, it can delay the LVDS clock to make the RX selection position of the input data look delay. If the right border is less than the left border, all LVDS data can be evenly delayed evenly, so that the LVDS clock and RX selection position of the data seem to be advanced in advance. In order to delay LVDS data or clock pair, the designer either increases the PCB tracking length or installs a capacitor between the LVDS transmitter and the receiver. It should be noted that when these technologies are used, all serial positions will evenly move to the right or left.

When the DS90CF386 or DS90CF366 receiver with a third -party OpenLDI transmitter is designed, users must calculate the budget budget (RSKM) based on the TX pulse position and RX selection position to ensure that the transmission is correct. For more information about calculating RSKM, please refer to the application description, the receiver of the channel link I and FPD link I devices (SNLA249).

Application curve

The following application curve is DS9Examples of the 0C385A series and DS90CF386 back -sequencer interface have a working frequency of 85 MHz, nominal temperature (25OC) and voltage supply (3.3 V).

Power recommendation

Correct power decoupling is very important for ensuring stable power supply and minimum power noise. Need to bypass electric containers to reduce the impact of switching noise, which may limit performance. For conservative methods, it is recommended to use three parallel -connected decoupled capacitors (multi -layer ceramic types on the surface) between each VCC (VCC, PLL VCC, LVDS VCC) and ground floor. The three capacitors are 0.1 μF, 0.01 μF, and 0.001μF, respectively. The size of the capacitor is 0402. Figure 28 shows an example. The designer should use wide power and ground lines, and ensure that each capacitor has its own ground plane pores. This helps reduce the overall inductance of the power filtering. If the circuit board space limits the number of bypass containers, the PLL VCC should receive the most filter. Next is the LVDS VCC pin, and finally the logical VCC pin.

Layout

Layout Guide

Like any high -speed design, circuit board designers must be able to repay high frequency and EMI performance through limitation To maximize the signal integrity that produces adversely impact reflexes and skewers. The following practice is a suggestion layout guide to optimize equipment performance.

ensure that the differential pair of the record channel is always tightly coupled to eliminate noise interference from other signals, and make full use of the co -model noise of the differential signal to offset the effect.

maintain equal length on the signal trajectory of the differential pair.

By reducing the number of holes in the signal trajectory to limit the impedance discontinuousness.

Eliminate any 90o corner on the trajectory, and use 45O elbow.

If you must exist on one signal polarity, you must use the perforated perforated in another polarity of the differential pair.

Different impedance of the selected physical media. The impedance should also match the connected terminal resistance value of the connected end resistance through the input terminal of the receiver.

If possible, use a short record of LVDS input.

layout example

The following figure shows the layout example of DS90CF386. The traces of blue correspond to the top layer, and the green traces correspond to the bottom layer. Please note that the DS90CF386 difference is tightly coupled to the input and close to the connector pin. In addition, observing the power supply container should be as close as possible to the pilot of the power supply as much as possible, and with a hole to minimize the inductance. In this layoutThe principle of explanation is also applicable to 48 -shot DS90CF366.