Features

Three regulatory output: core, I/O, and CLK combination

Integrated Intel Mobile 5 -digit VID DAC

No external current detection without external current detection The resistor

The outer MOSFET structure of the entire N channel

550kHz switch frequency will be outer

component size and cost

Integrate 150MA LDO linear regulator [123 ]

Low -level interruption current: lt; 100μA switch lacks phase operation to minimize CIN

Small 28 -pin narrow ssop package

] Intel's complete power controller

Mobile Pentium processor

Intel Mobile Pentium Core, I/O, clock power supply

Multi -logic power generator

LTC #174; 1705 is a complete power controller Intel Mobile Pentium processor. It includes two switching regulator controller, each designed to drive a pair of N -channel MOSFET to use voltage mode feedback, synchronize the buck structure, and provide core and I/O supply products. The core controller includes a 5 -bit DAC compliance with Intel Mobile VID specifications. IC also includes a low -voltage differential linear regulator (LDO), which can provide an output current up to 150 mA to provide CLK power.

Use a constant frequency of 550kHz PWM architecture to minimize the size of the external component and optimize the load transient performance. It provides a DC accuracy of 1.25%in its core output, 2%when I/0 and CLK output. The high -performance feedback circuit allows the circuit to maintain the total output under all transient conditions and adjust it within the range of ± 5%. The PGOOD logo of Ankai Road indicates that all three outputs are within the ± 10%range of its specified values. Close the circuit If the RUN/SS pin is pulled to the ground. In this mode, the LTC1705 power supply drops less than 100 μA.

Boostc – SWC , Boostio – SWIO 6 volts

Input voltage

SWC, SWIO -1V to 6V

Sensec, FBC, FBIO, Video -0.3V to (VCC+0.3V)

Okay, running /Ss,

IMAXC, IMAXIO to 3 volts (VC3V)

Peak output current lt; 10μs

TGC, BGC 5A level

TGIO, BGIO, BGIO, BGIO 1.25 Ann

Work temperature range (Note 2) –40 ° C to 85 ° C

Storage temperature range –65 ° C to 150 ° C

Lead temperature (welding (welding , 10 seconds) 300 degrees Celsius

Electricity

indicates the specifications suitable for the entire working temperature range, otherwise the specifications are TA 25 ° C.

Electric characteristics

indicates the specifications suitable for the entire working temperature range, otherwise the specifications are TA 25 ° C.

Note 1: The absolute maximum rated value means that the value device that exceeds life may be damaged.

Note 2: LTC1705 guarantees the performance specification from 0 ° C to 70 ° C. The operating temperature range between -40 ° C and 85 ° C are controlled by design, representation, and associations to determine statistical processes.

Note 3: The current of all entering device pins is positive; all the current output from the device is positive. Unless there are other regulations, all voltages are clearly stipulated in reference.

Note 4: PVCC and BVCC (VBOOST -VSW) must be greater than VGS (on) external MOSFET to ensure normal operation.

Note 5: The current supply current at normal runtime needs to charge the capacitor of the external MOSFET at the current current. This current changes with the power supply voltage and external choice.

Note 6: The power current when closed is controlled by the external MOSFET, which may be significantly higher than the static current, especially at high temperature.

Note 7: Design guarantee, without trial.

Note 8: The pressure loss is the minimum input output voltage to maintain the differential difference required for adjustment under the specified output current. In Dropout, the output voltage will be equivalent to Vinclk -vdropout.

Note 9: Each connected to VIDThe internal pull -ups of the input end have a series diode connected to the VCC to allow the input voltage to be no damage or clamping when the input voltage is higher than the VCC supply. (See Framemap.)

Note 10: Core feedback voltage accuracy is test by VSENSE to ensure output voltage accuracy test

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IMAXIO (pin 1): I/O power current limit settings. IMAXIO pin sets the current limit comparator threshold controller of I/O. If the voltage of the MOSFET at the bottom decreases, QBIO exceeds the current limit of the voltage value I/O controller at the IMAXIO. IMAXIO pins have a internal 10μA current source pulling, allowing the current to pass through the threshold of a single external resistor set to PGND. Cairin connects this current to QBIO. Reference current restriction programming chapters are more information about selecting the RIMAX value.

PVCC (pin 2): Drive power input. PVCC provides power supply for BGC and BGIO output drives. PVCC must be connected to a sufficiently high voltage to completely open the external MOSFETS QBC and QBIO. PVCC should generally be connected directly to VIN, the main system 5V power supply. PVCC requires at least 10 μF bypass electrical container directly PGND.

Boostc (pin 3): The power supply of the top department of the core controller. Boostc pins are powered by floating TGC driver. Use 1 μF capacitor to bypass the supercharger to SWC. The external Schottky diode created a complete floating charging pump from VIN to Boostc to supply power on the booster pump. No other needs external supply. Pifu CTIO S

BGC (pin 4): The core supply the top driver. BGC pin drives the bottom N -channel G gate synchronous switch MOSFET, QBC. The design purpose of the BGC is that the grid capacitance is as high as 10,000PF. If the SS/RUN becomes lower, the BGC becomes lower, and the QBC is turned off.

TGC (pin 5): The pile supply is driven. TGC pin drives the gate of the top N -channel MOSFET. This TGC driver obtains power from the BoostC pin and returns it to the SWC pin to provide QTC with a real floating driver. TGC is designed to drive a gate capacitance with up to 100,000pf. If RUN/SS becomes lower, TGC becomes lower and turn to QTC.

SWC (pin 6): core power exchange node. Connect SWC to the access node of the core converter. The TGC driver returns to SWC to SWC, switch to the top N -channel MOSFET, QTC. Electricity at SWCComparing the pressure through the current limit comparator and IMAXC, while the bottom MOSFET, QBC, is turned on.

PGND (pin 7): power supply ground. BGC and BGIO drivers return to this pin. The node QBC and QBIO, which connect PGND to the high current is close to the external MOSFET source, and VIN and VOUT bypass electrical containers

IMAXC (pin 8): core power current limit settings. See IMAXIO.

SS (Soft Start 9): Pull Run/SS to the outside of the GND and finally turn off the LTC1705 and turn off all external MOSFET switches. Static power supply current drops below 100 μA. The capacity of the capacitor core and I/O output from RUN/SS to GND -controlled voltage and the voltage when the rise rate of I/O output is powered on. When running/ss, the internal 3 μA current source is set to about 300ms/μF.

Compc (pin 10): Core controller loop compensation. Compc pins directly connect to the core controller error placing tolerator and PWM input comparator. Use RC networks and FBC pins between COMPC pins to compensate for the best transient response of the feedback loop.

FBC (pin 11): Core controller feedback input. Connect the ring compensation network of the core controller. The FBC is connected to the VID resistance network for setting the core output voltage.

GND (pin 12): signal ground. All internal low -power circuits return GND pins. Connect to low impedance grounding and is separated from PGND nodes. All feedback, compensation and soft start -up connections should return GND. GND and PGND should only be at a single point, near PGND pins and negative plate VIN bypass electrical containers.

Sensec (pin 13): core controller output induction. Connect to VOUTC

VID0 to VID4 (pin 14 to 18): VID programming input. These are logical input and are used to supply the pre -programming value in the pile (see Table 1). Video 4 is MSB and VID0 is LSB. VID selected code input is compliant with Intel Mobile VID specifications. Any VID code conversion will force PGOOD to reduce 20 μs. Each VID tube foot is connected in series (see the square diagram).

VCC (pin 19): power input. All internal circuits but the output drive is powered by this pin. Connect VCC to a low noise 5V power supply and bypass the foot. At least 10 μF capacitors are close to the LTC1705.

FBIO (pin 20): Input/output controller feedback input. Connect FBIO to set the output voltage through a resistor network. At the same time, connect the loop compensation I/O controller to the FBIO network.

comPIO (pin 21): I/O controller loop compensation.

pgood (pin 22): The power supply is good. PGOD is a logical output. If there is any one of the three power sources, PGOOD will lower the output exceeding the adjustment range (see the electrical characteristic table of the core, I/O, and CLK threshold). The external PGOOD needs to be pulled with a pull -up resistor to allow it to swing.

VOUTCLK (pin 23): clock power output. VOUTCLK is the output node of the internal linear clock power regulator. VOUTCLK provides a current CPU clock power of up to 150mA under 2.5V output power. At least 2.2 μF bypasses VoutCLK capacitors ground (refer to VCLK linear regulator section). If RUN/SS becomes lower, the VoutCLK regulator is closed.

Vinclk (pin 24): clock power input. Vinclk is the terminal of input internal linear CLK power regulator. Connect Vinclk to a 3.3V power supply to maximize efficiency. Weisk can be connected to the 5V power, but the VOUTCLK regulator is reduced. Use 10 μF to bypass the Vinclk capacitor to ground.

SWIO (pin 25): I/O controller exchange node. See SWC.

TGIO (pin 26): I/O controller top driver. See TGC. TGIO is usually designed as a gate capacitance driving up to 2000PF.

BGIO (pin 28): I/O controller's bottom driver. See BGC. The design of BGIO can usually drive a gate capacitance up to 2000PF.

LTC1705 includes two antihypertensive (antihypertensive) voltage mode feedback switch regulator controller and a low linear regulator. The three outputs were designed as the core, I/O, and CLK power supply Pentium system for Intel mobile devices. Each switching regulator controller EM uses a synchronous exchange structure, two of the external N channel MOSFETs of each channel. The chip works through a low voltage input power supply (maximum 6V), and provides high -power, high -efficiency, and accurately regulating the output voltage. Several characteristics of LTC1705 make it particularly suitable for micro -processor power adjustment. The core supply is very tight, and the initial accuracy and DC lines and load regulation are greater than 1.25%. The total adjustment of transient response is within 3.5%, and the circuit design is reasonable. The frequency of the 550kHz switch and the high -speed internal feedback amplifier allows the use of small physics, and lowering the importance of external components without affecting performance. 5 -bit DAC setting core output voltage, in line with intEl Mobile VID specification (Table 1). The internal benchmark of 800mv allows the adjustment output voltage to be low to 800mV, and no external level conversion amplifier. The linear regulator controls an internal P channel MOSFET, which can provide a current at a current of more than 150mA output voltage to 2.5V. Good power (PGOOD) When all three outputs are there, the sign has become high.

Step 2 conversion

The ""2 step"" structure uses a main regulator to convert the input power supply (battery or AC line voltage) intermediate power supply voltage, usually 5V. This intermediate voltage and then the voltage is converted into a system required for a system of low -voltage, high -current using auxiliary regulator (such as LTC1705). Two -step conversion eliminates a converter to convert a high input voltage output voltage, which is usually a clumsy design challenge. It also naturally incorporates the power supply part of its circuit part of its circuit or the change of the new circuit design, which can provide a current load of more than 5V capacity. Each regulator in a typical two -stage system remains relatively low (5: 1 or lower), operating efficiency at a higher speed, while maintaining a reasonable working cycle. In comparison, an input voltage of a regulator from the height 1.xv output must be required to weigh the external component values u200bu200bat the duty cycle ratio of the stenosis, while reducing efficiency and transmission response. Efficiency loss can exceed two steps. What makes calculations more complicated is that in fact, many systems turn off the total power supply of the middle 5V power supply and bypass the low -voltage power supply. Two -step solutions using LTC1705 usually match or exceed the single -step solution and provide additional benefits to improve the transient response, reduce the PCB area and simplify the power tracking routing.

Two -level adjustment can also obtain advantage management in thermal energy. The power consumption of the LTC1705 part of a 2 -step circuit is higher than a typical 1 -step converter, even if the total efficiency of the 1 -step converter is higher than the two -step method. In a typical microprocessor core power regulator, for example, the regulator is usually located in the central processor. The core regulator is located next to the already hot CPU, which exacerbates heat management. Designed in two -step LTC1705, a considerable proportion of power loss in the core adjustment system occurs in the 5V power supply is usually away from the CPU. The energy of thermal loss is relatively low in the LTC1705 system, minimizing the additional calories near the CPU.

Quick transient response

LTC1705 core and I/O power supply use fast 20MHz GBW computing amplifier as an error amplifier. This allows the compensation network design to have multiple poles and zero points compared with typical general car feedback, the configuration is more flexible amplifier. The high bandwidth of the amplifier, the frequency of the coupling switch is as high as 550kHz external electrical sensor and output capacitance value, allowing very high circular cross -frequency. In addition, a typical LTC1705 circuit is at a magnitude of 1 μH, allowing very fast DI/DT to transferMerchants. Results have superior transient response compared to traditional solutions.

High efficiency

LTC1705 core and I/O power supply use synchronous antihypertensive (buck) architecture, each output has two external N -channel MOSFETs. A floating upper part driver and a simple external charge pump provides the entire upper MOSFET to drive the entire MOSFET. The voltage mode feedback circuit and the MOSFET VDS current limit sensing circuit requires an external current response resistance to eliminate external components and corresponding power loss on the large current path. The correctly designed circuit using the low -grid charge MOSFET can improve the efficiency of more than 90%of the load current within the extensive output voltage range.

Video Programming

LTC1705 includes a airborne feedback network according to the Intel Mobile VID specification (Table 1). This network includes a variable value resistor and GND connected between Sensec and FBC and FBC. The values u200bu200bset by digital code settings appear at VID4: 0 pins. Connect Sensec to VOUTC to allow the network that monitor the output voltage. There is no additional feedback element to set the output voltage of the core controller, although the loop compensation component is still necessary. Each VIDN pin includes the internal 30K pull -up resistance, allowing it to float high, if there is no connection on the left. Pull the VCC connection resistor diode (see the square diagram), which allows the VIDN pin to pull to the top of the VCC without damage. Please note that code 01111 and 111111 are defined by Intel definition ""no CPU existence"