Features and Benefits

±2.5 A, 35 V output rating; low rds (on) output: 0.28Ω source, 0.22Ω sink, typical; automatic current decay mode detection/selection; 3.0 to 5.5 V logic supply voltage range; slow, fast, or mixed current Decay mode; home output; low power synchronous rectification; internal uvlo and thermal shutdown circuits; cross current protection.

The A3979 is a complete microstepping motor driver with built-in translator, designed as a pin-compatible replacement for the successful A3977, with enhanced microstepping (1/16 step) accuracy. It is designed to operate bipolar stepper motors in full-, half-, fourth-, and sixteen-order modes with output drive capacities up to 35 V and ±2.5 A. The A3979 includes a fixed off-time current regulator capable of operating in slow, fast or mixed decay modes. This current decay control scheme can reduce the audible noise of the motor, improve step accuracy, and reduce power consumption.

Translation is the key to A3979's ease of implementation. It allows a simple input of a pulse on the step pin to drive the motor one microstep, which can be a full step, half step, quarter step or sixteenth step, depending on the settings of the ms1 and ms2 logic inputs . There are no phase sequence tables, high frequency control lines or complex programming interfaces. The A3979 interface is ideal for applications where complex microprocessors are unavailable or overburdened.

Internal synchronous rectification control circuitry is provided to improve power consumption during PWM operation. Internal circuit protections include: hysteretic thermal shutdown, undervoltage lockout, and cross-current protection. No special power-up sequence is required.

The A3979 features a low profile (height ≤1.20 mm), 28-pin TSSOP, and exposed thermal pad. Packaged lead free, 100 % matte tin lead frame.

Function description

The A3979 is a complete micro-aircraft-stepper motor driver with a built-in converter for easy operation with minimal control wires. It is designed to operate bipolar stepper motors in full-step, half-step, fourth-step and sixteen-step modes. The current in each of the two output full bridges (all n-channel mosfets) is regulated by a fixed off-time pmw (pulse width modulation) control circuit. In each step, the current of each full bridge is set by the values of its external current sense resistor (rs1 or rs2), the reference voltage (vref), and the output voltage of its DAC (which in turn is controlled by the output of the converter).

At power-up or reset, the converter sets the DAC and phase current polarities to their initial initial state (as shown in Figures 2 to 5), and sets the current regulator to a mixed decay mode for both phases. When a step command signal appears on the step input, the converter automatically sequences the DAC to the next stage and current polarity. (See Table 2 for the current level sequence.) The microstep resolution is set by the combined effect of the inputs ms1 and ms2.

When stepping, if the next output level of the DACs is lower than the previous output level, the decay mode (fast, slow or mixed) of the active full bridge is set by the pfd input. If the next dac output level is higher than or equal to the previous level, the decay mode of that full bridge will be slow decay. This automatic current decay selection improves microstepping performance by reducing current waveform distortion due to motor back EMF.

Reset input ("R" or "E" or "S" or "E" or "T"). The R''E''S''E''T'' input (activating low) sets the converter to a predefined home state (shown in Figures 2 to 5) and turns off all dmos outputs. The main output goes low and all step inputs are ignored until the r∏e∏s∏e∏t∏ input is set high.

main output (main). The main output is an output indicator of the initial state of the logic translator. Once powered on, the translator will reset to the Home state (as shown in Figures 2 to 5).

Step input (step). A low-to-high transition step input puts the translator in sequence and advances the motor by one increment. The converter controls the input of the DAC and the current flow in each winding. The size of the increment is determined by the combined state of the inputs ms1 and ms2.

Microstep selection (ms1 and ms2). Inputs on terminals ms1 and ms2 select the microstep format as shown in Table 1. Any changes made to these inputs do not take effect until the next rising edge of the step command signal on the step input.

Direction Input (DIR). Internal PWM current control. The state of the DIR input determines the direction of rotation of the motor. Any changes made to this input do not take effect until the next rising edge of the step command signal on the step input. Each full bridge is controlled by a fixed off-time pulse-width modulated current control circuit that limits the load current to the desired value ittrip. Initially, a pair of diagonal source and sink MOS outputs are enabled and current flows through the motor windings and current sense resistor rs. When the voltage across r is equal to the dac output voltage, the current sense comparator resets the PWM latch. The latch then turns off the source mosfet (in slow decay mode) or the sink and source mosfet (in fast decay mode or mixed decay mode).

The maximum value of the current limit is achieved by selecting the voltages at the RS and VRF inputs, and the transconductance function is approximated by:

The DAC output reduces the VREF output to the current sense comparator in precise steps (see Table 2 for %ITRIMPax for each step).

It is critical that the maximum rating (0.5 V) on the SENSE1 and SENSE2 pins is not exceeded. For full step, VREF can be applied to the maximum rated value VDD, because the peak inductance value is 0.707 × VREF / 8. In all other modes, VREF should not exceed 4 V.

fixed rest periods. The internal pwm current control circuit uses a one-shot timer to control how long the mosfet remains off. The primary off-time toff is determined by the choice of external resistors rt and capacitors ct from each rc timing terminal to ground. The off time, over the range of CT = 470 pF to 1500 pF and rT = 12 KΩ to 100 KΩ, is approximately:

Reinforced concrete cutting. In addition to the fixed rest time in the pwm control circuit, the ctx device sets the blanking time of the comparator. This function will blank the output of the current sense comparator when the internal current control circuit switches the output. The comparator output is shielded to prevent false overcurrent detection due to reverse recovery current of the clamp diode or switching transients associated with load capacitance. Blank time can be approximated as:

Charge Pumps (CP1 and CP2). The charge pump is used to generate gate power greater than VBB to drive the source dmos gate. A 0.22µF ceramic capacitor should be connected between CP1 and CP2 for pumping purposes. In addition, a 0.22µF ceramic capacitor is required between vcp and vbb as a reservoir for the high-side dmos gate.

VREG (VREG). This internally generated voltage is used to operate the receiver side dmos output. The VREG pin must be separated from ground with a 0.22µF capacitor. VREG is internally monitored, and in the event of a fault, the device's DMOS output is disabled.

Enable input ("E", "N", "A", "B", "L", "E"). This valid low input

All DMOS outputs are enabled. When set to logic high, the output is disabled. The inputs to the converter (step, dir, ms1, and ms2) all remain active, independent of the input state.

closure. During normal operation, if a fault occurs, such as overheating (too high TJ) or undervoltage on the VCP, the output of the device will be disabled until the fault condition is removed.

At power-up, if VDD is low, an under-voltage lockout (UVLO) circuit disables the driver and resets the converter to its initial state.

Sleep mode ("S", "L", "E", "E", "P"). This low control input is used to minimize power consumption when the motor is not in use. It disables many internal circuits, including output DMOS FETs, current regulators, and charge pumps. Setting this to logic high allows normal operation and startup (where the A3979 drives the motor to the initial microstep position). To allow the charge pump (gate drive) to stabilize when the device comes out of sleep mode, a 1 ms delay is provided before the step command is signaled to the step input.

Fast decay input percentage (pfd). When the output current commanded by the step input signal is lower than the previous step, it switches the output current decay to slow, fast or mixed decay mode, depending on the voltage level of the pfd input. If the voltage at the pfd input is greater than 0.6 × vdd, the slow decay mode is selected. If the voltage at the pfd input is less than 0.21 × vdd, the fast decay mode is selected. When the vpfd is between these two levels, select the mixed decay mode, as described in the next section. This terminal should be connected with a 0.1µf capacitor.

Mixed decay operations. If the voltage at the pfd input is between 0.6 × vdd, the bridge operates in mixed decay mode, determined by the step sequence (as shown in Figures 2 to 5). When the trigger point is reached, the device enters a fast decay mode until the voltage on the RCX terminal decays to the same level as the voltage applied to the PFD terminal. The time that the device operates in rapid decay is approximately:

After this fast decay portion, the device switches to slow decay mode for the remainder of the fixed off period.

Synchronous rectification. When the PWM is off-period is triggered by an internal fixed-off time period, the load current cycles according to the decay mode selected by the control logic. The A3979 synchronous rectification function turns on the appropriate mosfet during current decay and effectively shorts the body diode using a low rds(on) driver. This greatly reduces power dissipation and eliminates the need for external Schottky diodes for most applications. Synchronous rectification can be set to active mode or disabled mode: when the sr input is logic low, active mode is enabled and synchronous rectification may occur. This mode prevents load current reversal by turning off synchronous rectification when a zero current level is detected. This prevents reverse conduction of the motor windings. active mode

application information

When the SR input is logic high, synchronous rectification is disabled. This mode is typically used when an external diode is required to transfer power dissipation from the a3979 package to the external diode.

layout. The printed circuit board on which the device is mounted should have a heavy duty ground plane. For best electrical and thermal performance, the A3979 should be soldered directly to the board.

The load power terminal vbbx should be separated from the electrolytic capacitor (more than 47μf recommended) and placed as close to the device as possible.

To avoid problems due to capacitive coupling of high dv/dt switching transients, move the bridge output traces away from the sensitive logic input traces. Always drive logic inputs with low source impedance for improved noise immunity.

ground. The agnd (analog ground) terminal and the PGND (power ground) terminal must be connected together externally.

All ground wires should be connected together and as short as possible. A device-centric satellite-to-earth system is the best design.

The copper ground plane located under the exposed thermal pad is usually used as the star ground.

current sensing. To minimize inaccurate sensing of output current levels caused by ground tracking IR drops, the current sense resistor rs should have a separate ground return to return to the device's star ground. This path should be as short as possible.

For low value sense resistors, the IR voltage drop across the printed circuit board sense resistor trace can be large and should be considered. Sockets should be avoided because the contact resistance of the socket will cause a change in RS: RS = 0.5/ITRIPmax

Thermal Protection. Typically, this internal circuit shuts down all drivers when the header temperature reaches 165°C. Its purpose is only to protect the device from faults caused by excessive connection temperature and should not imply that the output is short-circuited. Thermal shutdown has a hysteresis of about 15°C.