Overview
The W29GL 128 C parallel flash memory provides a storage solution for embedded system applications requiring better performance, lower power consumption and higher density. The device has random access speeds of 90ns, fast page access speeds of 25ns, and program and erase times are also much faster than what's currently on the market. The W29GL128C also provides special features such as a compatible manufacturer ID that makes the device an industry standard
Compatible, no firmware changes required.
2 Features
8226 ; – A total of 128 unified sectors 64K words/128K bytes unified sector architecture•. 32-word/64-byte write buffer – reduces total program time for multiple word updates•. 8-word/16-byte page read buffer •. Secure Silicon Field – programmed and locked by customer or during production – 128-word/256-byte sector, permanent secure identification with 8-word/16-byte random electronic serial number•. Powered and independent bodies with enhanced sector protection •. The polling/toggle method is used to detect program status and erase operations•. Suspend and Resume commands • for program and erase operations. Over 100,000 erase/program cycles•. 20+ years of data retention•. Software and Hardware Write Protection – Write protect all or part of memory – Enable/disable protection using WP pin – Top or bottom array protection•. Low power consumption •. Deep Power Down Mode •. Wide temperature range • – Compatible manufacturer IDs that can be replaced without firmware changes
•. Faster Erase and Program Times – Erase 1.5x faster than industry standard – Program 2x faster than industry standard – Allows for increased production throughput and faster field updates•. Supports CFI (Common Flash Interface)
•. Single 3V Read/Program/Erase (2.7-3.6V)
•. Enhanced Variable IO Control – All input levels (address, control and dq) and output levels are determined by the voltage on the evio input. evio ranges from 1.65 to vcc
•. #WP/ACC Input – Speeds up programming time (when using VHH) to improve throughput during system production – Protects the first or last sector regardless of sector protection settings•. Hardware reset input (reset) to reset the device •. A ready/busy output (ry/by) detects program completion or erase cycles•. Package

block diagram

Read Array Data The default state after a power-up or reset operation is read mode.
To perform a read operation, enable the chip by setting "CE", "OE active" and "WE high". Also, provide the desired address or status register location on the address line. After satisfying the TCE and toe-in timing requirements, the system reads the content of the addressed location on the data IO pin. If the device or its outputs are not enabled by a high CE or OE, the output data on the data IO pins will not be accessible and the outputs will remain tri-stated.
When the device successfully completes an embedded memory operation (i.e. program, automatic chip erase, or sector erase), it returns to read mode and reads data from any address in the memory array. However, if the embedded operation fails to complete, by verifying that the status register bit dq5 (time limit exceeded flag) goes high during the operation, the system should perform a reset operation to return the device to read mode.
Some operational states require a reset operation to return to read mode, for example:
• A time-out condition during a program or an erase fail condition is indicated by bit DQ5 of the Run-time Status register going high. Failure in either state prevents the device from automatically returning to read mode.
• During device auto-select mode or CFI mode, a reset operation is required to terminate its operation.
In both cases above, the system will not be able to read the array data unless a reset operation (hardware reset or software reset instruction) is performed, the device will not return to read mode.
If the device receives an Erase Suspend command in a sector erased state, the device will enter Erase Suspend Read mode. Erase operations will be suspended (after a time delay of not more than 20 microseconds) before entering Erase Suspend Read Mode. At this point, data can be programmed or read from any sector that has not been erased. Another way to verify the state of the device is to read the address within the erased sector. This will only provide the contents of the status register.
Program operations in Erase Suspend Read Mode for valid sectors will automatically return to Erase Suspend Read Mode when the program operation completes successfully.
The Erase Resume instruction must be executed to exit Erase Suspend Read mode, at which point the suspended erase operation will resume. Unless another Erase Suspend command is received, the Erase operation will continue where it left off until it completes successfully.
Page Mode Reads Page mode reads have a page size of 16 bytes or 8 words. The higher address a[22:3] accesses the desired page. To access a specific word or byte in a page, select word mode via [2:0] and byte mode via [2:0, A-1]. Page mode can be turned on by leaving the "page read address" unchanged and changing the "internal read page" address. Page access time is taa or tce, then tpa for page read time. When CE switches, the access time is TAA or TCE.
A device reset operation that pulls the reset pin low for a time equal to or greater than trp will return the device to read mode. If the device is executing a program or wipe operation, the reset operation will take up to a period of time1 before the device returns to read mode. The Ry/by pin will remain low (busy state) until the device returns to read mode.
Note that the device will draw more current if the reset pin is held at a voltage greater than GND+0.3V and less than or equal to VIL. When the reset pin is held at GND±0.3V, the device only consumes reset (ICC5) current.
It is recommended to connect the system reset signal to the reset pin of the flash memory. This allows the device to reset with the system and put it in a state where the system can immediately start reading boot code from it.
A reset command is executed to reset the device back to read mode under the following conditions:
• During the erase instruction sequence, before the complete instruction set completes.
• Sector erase timeout period • Erase fails when DQ5 is high.
• During a program instruction sequence, including erase pending program instructions, before the complete instruction set is complete.
• The program fails while DQ5 is high and the Erase Suspend program fails.
• Auto-select mode • CFI mode • When the device is in auto-select mode or CFI mode, or when there is a program or erase fault (DQ5 high), the user must issue a reset command to reset the device back to read mode.
• When the device performs a program (non-program fail) or erase (non-erase fail) function, the device ignores the reset command.
Standby Mode Standby mode is entered when both reset and CE are driven to VCC ±300mV (inactive). At this point, regardless of the state of the WE or OE pins, the output pins are in a high impedance state and the device will draw minimal standby current (ICC4). If the device is deselected during an erase or program operation, the device will draw active current until the operation is complete.
output disable mode
The oe pin controls the state of the data io pin. If oE is driven high (VIH), all data IO pins will remain high impedance, if driven low, the data IO pins will drive data (oE has no effect on the ry/by output pins).
Write Operation To perform a write operation, the chip enable (CE) pin is driven low and the output enable (OE) is pulled high to disable the data IO pins to a high impedance state. The required address and data should appear on the corresponding pins. The address is latched on the falling edge of "us" or "us" and the data is latched on the rising edge of "us" or "us". To see an example, refer to the timing diagrams in Figure 8-5 and Figure 8-15. If an invalid write instruction (not defined in this datasheet) is written to the device, it may leave the device in an undefined state.
Byte/Word Select To choose between byte or word mode, the byte input pin is used to select how data is input/output on the data IO pins and the organization of the array data. If the byte pin is driven high, word mode is selected and all 16 data IO pins will be active. If byte is pulled low, byte mode will be active and only data IO DQ[7:0] will be active. The remaining data IO pins (DQ[14:8]) will be in a high impedance state and DQ15 becomes the A-1 address input pin.
Automatic programming of memory arrays To program memory arrays in byte or word mode, refer to the instruction definition table for the correct cycle-defining instructions, these include 2 unlock instruction cycles, a0h program cycle instruction, and include the specified address location and subsequent cycles of the desired data content of a byte or word. Then start the embedded algorithm to automatically program the array.
Once the sequence of program instructions is executed, the internal state machine begins executing the algorithms and timing required for programming and cell verification. This operation includes generating suitable program pulses, checking cell threshold voltage (VT) margins, and if any cells fail verification or have acceptable margins, the repeated sequence of program pulses will loop again. An internal processing mechanism will prevent cells that pass the margin and verify tests from being overprogrammed by disabling further program pulses through the cell, as failing cells will continue to run through the internal programming sequence until they pass.
This feature allows the user to perform an automatic programming sequence only once, with the device state machine taking care of the programming and verification process.
Array bits during programming can only change the bit state "1" (erased state) to "0" (programmed state). The reverse operation cannot be performed with a programmed operation. This can only be done by performing an erase operation first. Remember that the internal write verify only checks and detects errors if a "1" is not successfully programmed to a "0".
During the embedded programming algorithm, any commands written to the device are ignored, except for hardware reset or program suspend instructions. A hardware reset will terminate program operation after a period of not more than 10 microseconds. In the event of a program suspend, the device will enter program suspend read mode. When the embedded program algorithm completes or a hardware reset terminates the program, the device returns to read mode.
Once the embedded program operation begins, the user can check for completion by reading the following bits in the status register:
Polling note one during embedded program operation. Ry/by is an open-drain output pin and should be connected to VCC through a high value pull-up resistor.
Erase Memory Array Sector Erase and Chip Erase are two possible erase operations performed on the memory array. A sector erase operation erases one or more selected sectors, which can occur simultaneously. A chip erase operation erases the entire memory array except for any protected sectors.
Sector Erase The Sector Erase operation returns all selected sectors in memory to a "1" state, effectively erasing all data. This operation requires six instruction cycles to start the erase operation. The unlock sequence is the first two cycles, followed by the configuration cycle, the fourth and fifth are also "unlock cycles", and the sector erase command is the sixth cycle. Once the sector erase command sequence is complete, an internal 50 microsecond timeout counter is started. During this time, additional sector address and sector erase commands can be issued, allowing multiple sectors to be selected and erased simultaneously. Once the 50 microsecond timeout counter reaches its limit, no additional command instructions will be accepted and the embedded sector erase algorithm will begin.
Note that the 50 microsecond timeout counter restarts after each sector erase command sequence. If any command other than Sector Erase or Erase Suspend is attempted during the timeout, the device will abort and return to read mode.
Once the embedded sector erase algorithm starts, all instructions except Erase Suspend or Hardware Reset are ignored. A hardware reset will abort the erase operation and return the device to read mode.
Polling Notes During Embedded Sector Erase Operation
1. The dq3 status bit is a 50 microsecond timeout indicator. When dq3=0, the 50 microsecond timeout counter has not reached zero, and a new sector erase command can be issued to specify the address of another sector to be erased. When dq3=1, the 50 microsecond timeout counter has expired and the sector erase operation has begun. Erase Suspend is the only valid instruction that may be issued once an Embedded Erase operation is in progress.
2. Ry/by is an open-drain output pin and should be connected to VCC through a high value pull-up resistor.
3. When attempting to erase only protected sectors, the erase operation is aborted, preventing any data changes in the protected sectors. DQ7 will output a "0" and DQ6 will toggle briefly (100 microseconds or less) before aborting and returning the device to read mode. However, if unprotected sectors are also specified, they will be erased normally and protected sectors will remain unchanged.
4. dq2 is a localized indicator that shows whether an erase operation is in progress for the specified sector. dq2 toggles when the user reads at the address where the sector is being erased (in erase mode) or to be erased (in erase suspend mode).
Chip Erase A chip erase operation returns all memory locations that contain bit state "0" to a "1" state, effectively erasing all data. This operation requires six instruction cycles to start the erase operation. The unlock sequence is the first two cycles, followed by the configuration cycle, the fourth and fifth are also "unlock cycles", and the sixth cycle initiates the chip erase operation.
Once the chip erase algorithm has started, no other instructions will be accepted. However, if a hardware reset is performed or the operating voltage falls below an acceptable level, the chip erase operation will terminate and automatically return to read mode.
The embedded chip erase algorithm status can be verified by:
Polling Notes During Embedded Chip Erase Operation
Ry/by is an open drain pin and should be connected to VCC through a high value pull-up resistor.
Clear Suspend/Resume If a sector erase operation is in progress, the Erase Suspend command is the only valid command that may be issued. Once the Erase Suspend command is executed during the 50 microsecond timeout period following the Sector Erase command, the timeout period will expire immediately and the device will enter Erase Suspend Read mode. If an Erase Suspend command is executed after a sector erase operation has started, the device will not enter Erase Suspend Read Mode until approximately 20 seconds (5 seconds typical) has elapsed. To determine that the device has entered Erase Suspend Read mode, use dq6, dq7, and ry/by status to verify the status of the device.
Once the device enters Erase Suspend Read mode, any sector can be read or programmed except those erased by the erase operation. When attempting to read a sector scheduled to be erased or programmed in suspend mode, only the contents of the status register are present. Before issuing another erase command, a restore command must be executed and it is recommended to check the state of the DQ6 toggle bit.
Status register bits can be verified to determine the current state of the device:
Polling During Embedded Erase Suspend In Erase Suspend mode, in addition to sector and chip erase, instruction sets such as read silicon id, sector protection verification, program, cfi query, and erase recovery can be performed.
Sector Erase Resume The Sector Erase Resume command is a valid command only in Erase Suspend Read Mode. Once erase resumes, another erase suspend instruction can be executed, but a 400 microsecond gap is allowed between erase resume and the next erase suspend instruction.
Program Suspend/Resume Program Suspend is the only valid instruction that may be executed once program operation is in progress. After executing a program suspend instruction, you can verify that the device has entered program suspend read mode by checking ry/by and dq6. Programming should stop at 15µs maximum (5µs typical).
Any sector can be read, except those that are suspended by the program. Attempting to read a sector where the program is suspended is invalid. Before performing another program operation, the resume instruction must be executed and the DQ6 toggle bit state must be verified. Use the status register bits shown in the following table to determine the current state of the device:
Program Suspend Read Program Suspend Sector Polling During Embedded Program Suspend In Program/Erase Suspend mode, instruction sets such as read silicon id, sector protection verification, program, cfi query can also be executed .
Program Resume The program resume instruction is valid only when the device is in program suspend mode. After the program resumes, another program suspend instruction can be executed. Make sure there is at least a 5 microsecond interval between program resumption and the next pending instruction.
Write Buffer Programming Operation Write Buffer Programming Operation to program 64 bytes or 32 words in a two-step programming operation. To start performing write buffer programming, start with the first two unlock cycles, write the third cycle to the programmed sector address destination, and then write the buffer load instruction (25h). The fourth cycle repeats the sector address while the write data is the expected number of word locations to be written minus one. (For example, if the number of word locations to write is 9, the value will be 8h.) The 5th cycle is the first starting address/data set. This will be the first pair to be programmed and subsequently, set the "write buffer page" address. The cycle 5 format is repeated for each additional address/data set to be written to the buffer. Remember that all collections must stay within the write buffer page address range. Otherwise, the operation will abort.
The second step is to program the contents of the write buffer page. This is done with one cycle containing the sector address used in step 1 and the "Write Buffer Program Confirm" instruction (29h).
Standard suspend/resume commands can be used during write buffer operations. Also, once the write buffer programming operation is complete, it returns to normal read mode.
Write buffer programming can be done in any order. However, CFI functions, automatic selection, secure silicon sectors do not work while the program is running. Multiple write buffer programming operations within the same write buffer address range are accessible without intervening erase. No bit in the address range of the write buffer can be programmed from 0 back to 1.

Buffer Write Abort The write buffer programming sequence is aborted if:
• During "number of locations to program", the word count minus the one loaded is greater than the page buffer size (32).
• The written sector address is different from the sector address specified during the write buffer load command.
• If the address/data set is not within the write buffer page range set by the first initial write buffer page of loop 5, select the address/data set.
• There is no "Program Confirmation Command" after the specified number of "Data Load" cycles.
After the write buffer is aborted, the status register will be dq1=1, dq7=data 35; (the last loaded address), dq6=toggle, dq5=0. This state indicates that the write buffer programming operation has been aborted. The reset command sequence must be aborted by writing to the write buffer to reset the device back to read array mode.
Polling Buffer Write Abort Flag Accelerated Programming Operation By applying high voltage (VHH) to the WP/ACC pin, the device will enter accelerated programming mode. The accelerated programming mode allows the system to directly skip the normal unlock sequence instructions and program byte/word locations. The current drawn from the wp/acc pin during accelerated programming is no longer iacc1. Important: No more than 10 accelerated programs per department. (For any other function, other than programming or possible damage to the device, wp/acc should not be kept at vhh.)
Auto-Select Bus Operation There are basically two ways to access the auto-select operation; the auto-select command is applied to the A9 via a software command and a high voltage. For details on equivalent instruction operations that do not require the use of VHH, see Auto-Select Instruction Sequences later in this section. The following five bus operations require A9 to be upgraded to VHH.
Sector Lock Status Verification To verify the protected status of any sector using bus operations, perform a read operation applying VHH to A9, the sector address on address pins A[22:12], address pins A6, A3, A2, and A0 remain low, and address pin A1 remains high. If dq0 is low, the sector is considered unprotected; if dq0 is high, the sector is considered protected.
Read Silicon Manufacturer ID Code
Winbond's 29GL series of parallel flash has an industry standard compliant manufacturer ID code of 01H. To verify the silicon manufacturer ID code, perform a read operation under VHH applied to pin A9, and address pins A6, A3, A2, A1, and A0 are held low. Then, the id code[7:0] can be read on the data bits dq.
Read Silicon Device ID Code To verify the Silicon Device ID code, perform a read operation, apply VHH to the A9 pin, address pins A6, A3, A2, A1 and A0 with multiple bit combinations to return the Winbond Device ID code 7eh, 21h, or 01h, as indicated by data bits Dq[7:0].
Security sector high and low address read indication bit DQ7
To verify that the secure sector is locked at the factory, perform a read operation with VHH applied to A9, address pins A6, A3, and A2 are held low and address pins A1 and A0 are held high. If the secure sector is factory locked, the code 99h (highest address sector) or 89h (lowest address sector) will appear on data bits dq[7:0]. Otherwise, the factory unlock code 19H(H)/09(L) will be displayed.
Autoselect Operations The autoselect instructions shown in Table 7-13 can be executed if the device is in one of the following modes: Read, Program Suspend, Erase Suspend Read, or cfi. At this point, the user can issue (two unlock cycles followed by the auto-select command 90h) to enter the auto-select mode. Once in the auto-select mode, the user can query the manufacturer id, device id, secure sector lock status or sector protection status multiple times without executing the unlock cycle and the auto-select instruction (90h) again.
Once auto-select mode is entered, executing the reset instruction (f0h) will return the device to the active mode it left when auto-select mode was first executed.
Another way to enter the auto-select mode mentioned earlier is to use one of the bus operations shown in Table 7-2 in a device bus operation. Once the high voltage (VHH) is removed from the A9 pin, the device will return to the active mode it left off when the autoselect mode was first executed.
The purpose of the automatic selection command sequence The purpose of the automatic selection mode is to access the manufacturer ID, device ID, and verify that the security silicon is locked and the sectors are protected. There are four instruction cycles that make up the auto-select mode. The first two cycles are the write unlock command, followed by the autoselect command (90h). The fourth cycle is the read cycle, and the user can read any number of times at any address without entering another instruction sequence. A reset command is necessary in order to exit auto-select mode and return to reading the array. When auto-select mode is selected, no commands other than reset commands are allowed to auto-select MFR/Device ID/Secure Silicon/Sector Protection Read Enhanced Variable IO (EVIO) Control Enhanced Variable IO (EVIO) Control Allows the host The system sets the voltage levels that the device generates and tolerates on all inputs and outputs (address, control, and DQ signals). The evio range is 1.65 to vcc.
For example, a 1.65-3.6 volt EVIO allows I/O at 1.8 or 3 volt levels, driving and receiving signals from other 1.8 or 3 volt devices on the same data bus.
Hardware Data Protection Options Hardware data protection is the second of the two main sector protections offered by the W29GL128.
The WP/ACC option is protected from all erase/program operations by setting the wp/acc pin to vil, the highest or lowest sector (device specific). If wp/acc is set high, the top and bottom sectors will revert to their previous protected/unprotected state.
Note: When the device enters standby mode, the maximum input load current increases if the wp/acc pin is at vih.
VCC write protection When VCC is less than VWPT (VCC write protection threshold), this device will not accept any write commands. This prevents inadvertent data changes during power up, power down, temporary power down, or VCC low. If vcc is lower than vwpt, the device automatically resets itself and ignores write cycles until vcc is greater than vwpt. Once VCC rises above VWPT, ensure that the correct signal is present on the control pins to avoid accidental program or erase operations.
Write Pulse "Failure" Protection Pulses less than 5ns are treated as failures of the control signals "ce", "we" and "oe" and will not be considered a valid write cycle.
A power-on write inhibit device ignores the first instruction on the rising edge of "we" if "we" and "ce" are set to vil and "oe" is set to vih when the device is powered up.
Logical suppression When ce is in vih, we are in vih, or oe is in vil, the write loop is ignored. A valid write cycle requires OE on CE and VIH.
Inherent data protection device built-in mechanism will reset to read mode during power up to avoid accidental erasing or programming.
Instruction completion of an invalid instruction set will cause the memory to return to read mode. The device will not begin erasing or programming operations until the valid instruction set is successfully completed.
Power-Up Sequence During power-up, the device is in read mode.
Power Supply Decoupling To reduce noise effects, it is recommended to connect a 0.1µF capacitor between VCC and GND.
Enhanced Sector Protection/UN Protection The unit is factory set in the individual protection mode of the Enhanced Sector Protection scheme. Users can disable or enable program or erase operations for any single sector or the entire chip. The diagram below helps to describe an overview of these methods.
The device defaults to standalone mode, with all sectors unprotected from the factory.
The following flowchart shows the detailed algorithm for enhanced sector protection:

Enhanced Sector Protection/Unprotected IPB Program Algorithm Lock Register The user can select the secure silicon sector protection bit as the secure sector protection method by setting the lock register bit dq0. The lock register is a 16-bit one-time programmable register. Once DQ0 is programmed, it is permanently locked in this mode.
Once the instruction set entry instruction sequence for the lock register bits is issued, all sector read and write functions are disabled until the lock register exit sequence is executed.
Memory sector and extended memory sector protection is configured using lock registers

Lock Register Program Algorithm Individual (Non-Volatile) Protection Mode Individual Protection Bit (IPB)
An Individual Protection Bit (IPB) is a non-volatile bit, one bit per sector, with persistence equal to that of a flash array. IPB pre-programming and verification are managed by the device prior to erasing, so no monitoring is required.
Each protection bit is set sector by sector by IPB program instructions. Once IPB is set to "0", the linked sector will be protected from any program and/or erase functions on that sector. IPBs cannot be erased individually, but executing the "ALL IPB ERASE" instruction will erase all IPBs at the same time. Read and write functions are disabled when IPB programming is performed on all sectors until the mode is exited.
If one of the protected sectors needs to be unprotected, first, the IPB lock bit must be set to "1" by doing one of the following: power off the device or perform a hardware reset. Second, the "ALL IPB ERASE instruction needs to be executed. Third, the individual protection bits need to be set again to reflect the desired settings, and finally, the ipb lock bits need to be set again, which locks the individual protection bits, and the device works normally again.
To verify the IPB programming status of a given sector, an IPB read instruction needs to be executed on the device. See the IPB program algorithm flow chart below for details.
NOTE• When the IPB lock bit is set, program and/or erase instructions will not execute and time out without programming and/or erasing the IPB.
• For best protection, it is recommended to execute the IPB Lock Bit Set instruction early in the startup code. Also, protect the boot code by keeping wp 35;/acc=vil. Note that the ipb and dpb bits do the same thing when wp/acc=vhh and wp/acc=vih.
• In IPB command mode, reading within this sector will restore the IPB status of that sector. All reads must be performed in read mode.
Issuing an IPB instruction set exit will reset the device to normal read mode, enabling reads and writes to the array.
Dynamic Protection Bit (DPB)
Dynamic protection allows software applications to easily protect sectors from accidental changes, however, the protection can be easily disabled when changes are required.
All dynamic protection bits (dpb) are individually linked to their associated sectors, and these volatile bits can be individually modified (set or cleared). dpb provides a protection scheme only for unprotected sectors with the associated ipb cleared. To change the DPB, a "DPB Instruction Set Entry" must be executed, followed by a DPB Set (Program to "0") or DPB Clear (Erase to "1") command. This puts each sector into a protected or unprotected state. To exit DPB mode, execute the "DPB instruction set exit" instruction.
Note • IPB is cleared (cleared to "1") when parts are first shipped, DPB can be set or cleared after power up or reset.

IPB program algorithm notes one. IPB program/erase status polling flow: Check DQ6 switching, when DQ6 stops switching, the read status is 0H/01H (0h for program and 01h for erase), otherwise the status is "failed" and "exit".
Individual Protection Bit Lock Bit The Individual Protection Bit Lock Bit (IPBLK) is a global lock bit that controls the state of all IPBs. It is a single volatile bit. If ipblk("0") is set, all ipbs are locked and all sectors are protected or unprotected according to their respective ipbs. When IPBLK=1 (clear), all IPBs are unlocked and allowed to be set or cleared.
To clear the IPB lock bit, a hardware reset or power cycle must be performed.

Sector Protection Status Table Secure Sector Flash Area An additional 128 words of storage space is used as a secure sector area that can be factory locked or customer locked. To query the lock status of the device, customers can issue Secure Sector Protection Verification or Secure Sector Factory Protection Verification using auto-select address 03H and DQ7.
The secure sector area is unprotected at the factory and the secure silicon indicator bit (DQ7) is set to '0' for customer lockable devices. The secure sector area is protected at the factory and the secure silicon sector indicator bit is set to '1' for factory locked devices.
Factory Locked: The security sector is programmed and secured at the factory. In a factory locked device, the security sector is permanently locked by the ESN before shipment from the factory. It occupies addresses 00000H to 0000FH in byte mode and 00000H to 00007H in word mode because the device There is a 16-byte (8-word) ESN (Electronic Serial Number) in the secure area.