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The support of VivadoHLS for OpenCV does not mean that the OpenCV function library can be directly synthesized into RTL code, but the code needs to be converted into synthesizable code. These synthesizable video libraries are called HLS video libraries, provided by VivadoHLS.

And for performance reasons, the architecture based on OpenCV is more complex and consumes more power. OpenCV image processing is built on the memory frame cache, it always assumes that the video frame data is stored in the external DDR memory, therefore, OpenCV has poor performance for accessing local images, because the processor's small cache performance is not enough to complete this Task. OpenCV seems to be sufficient for many applications when the resolution or frame rate requirements are low, or when processing the required features or regions in larger images, but for high-resolution high-frame-rate real-time processing scenarios, It is difficult for OpenCV to meet the demands of high performance and low power consumption.

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The VivadoHLS video library is used to replace many basic OpenCV functions. It has similar interfaces and algorithms to OpenCV. It is mainly aimed at image processing functions implemented in the FPGA architecture, and includes FPGA-specific optimizations, such as fixed-point operations instead of floating-point operations. (Not necessarily accurate to bits), on-chip line buffer (line buffer) and window buffer (window buffer). Figure 2.1 shows the system architecture for implementing video processing on a Xilinx Zynq AP SoC device.

The full programmability of the Zynq-7000 enables automakers and automotive electronics suppliers to not only accelerate time-to-market and focus on product innovation, but also reprogram products in response to changing standards and regulatory requirements. This powerful combination significantly improves performance relative to solutions that require multiple chips. The Xilinx Zynq-7000 All Programmable SoC family is the industry's first SoC family to integrate an ARM dual-core Cortex-A9 MPCore processing system and tightly integrated programmable logic on a single chip. Achieving the same level of performance with a multi-chip solution increases cost, complexity, and power consumption.

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The VivadoHLS video processing library uses the hls::Mat<> data type, which is used to model the processing of video pixel streams, and is essentially equivalent to the hls::steam<> stream type, rather than stored in external memory in OpenCV. matrix matrix type. Therefore, in the design of OpenCV with VivadoHLS, it is necessary to modify the input and output HLS synthesizable video design interface to the Video stream interface, that is, use the video interface provided by HLS to synthesize the function to realize AXI4 video stream to VivadoHLS in hls ::Mat<> type conversion.

However, at 7nm, FPGA speed and density are greatly increased, and power consumption is also lower, so this competitive landscape may change, especially for ASICs and FPGAs. Intel's 10nm is still delayed, allowing Xilinx to dominate the FPGA market after acquiring Altera, in addition to the cloud market that Intel is focusing on. Split the SoC prototyping and emulation market. Flexibility and adaptability are the main selling points of ACAP. Especially in the era of artificial intelligence, Xilinx also hopes to realize the future of Intel and Nvidia through this advantage. Apparently this applies to Intel and Nvidia. The introduction of ACAP will help Xilinx compete with higher-level competitors in new markets. The competition between FPGAs and ASICs will continue.