XCS30XL-4PC84C_XQ2VT40-5FG676M Introduction

In fact, a similar plot was staged as early as 2015, when Intel (Intel) acquired FPGA manufacturer Altera for $16.7 billion, and Altera also followed the trend for Intel's follow-up "CPU+xPU (GPU+FPGA+ASIC+ eASIC)” strategy provides the most solid foundation. On the other hand, AMD and Xilinx have been working closely together for a long time. A series of storage system-oriented IPs such as NVMe HA, NVMe TC and Embedded RDMA previously provided for AMD EPYC (Xiaolong) data center processors can help AMD build low latency The high-efficiency data path, thus realizing the efficient storage acceleration function of FPGA.

It combines a scalar engine representing a processor system (PS), an adaptive engine representing a programmable logic (PL), and an intelligent engine using a high-bandwidth network-on-chip (NoC). The Versal Adaptive Compute Acceleration Platform (ACAP) is the latest generation of Xilinx devices built on TSMC's 7nm FinFET process technology.

XCS30XL-4PC84C_XQ2VT40-5FG676M

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In response to AMD's acquisition of Xilinx, the Wall Street Journal analyzed that AMD may use its high stock valuation as a bargaining chip to promote the transaction or delist Xilinx at a high price. AMD’s stock price has soared 89% this year, and its market value has now exceeded $100 billion to $101.568 billion.

. But in recent years, AMD's data center processor business has been growing, and the competition with Intel, which has long dominated the field, has become increasingly fierce. The addition of Xilinx will put AMD in a better position to compete with Intel. , and capture a larger share of the fast-growing telecom and defense markets.

Among the four products, the flagship processor is the Ryzen 9 5950X, which is the same as the Ryzen 9 3950X, with dual CCD modules, 16 cores and 32 threads, 8MB L2 cache, and 64MB L3 cache, of which the L3 cache is from four 16MB blocks. It has become two pieces of 32MB, which are shared by 8 cores respectively. The maximum acceleration frequency has increased from 4.7GHz to 4.9GHz, and the base frequency is 3.4GHz.

Unlike standard chips, they can be reprogrammed after production. This makes them highly valuable in rapid prototyping and rapidly emerging technologies. In the FPGA space, Intel is another major player, having established itself in the space with its 2015 acquisition of Altera. Xilinx, mostly known as microchips called Field Programmable Gate Arrays (FPGAs), is the leading company in this field.

XCS30XL-4PC84C_XQ2VT40-5FG676M

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Even in the chip design of cpu and other chip giants such as Xilinx and intel, they will first simulate on the fpga, and then perform the streaming processing of the chip, not to mention the AI-specific chips launched by many AI algorithm companies in recent years. . In 2013, the global FPGA market size was $4.563 billion, and by 2018, this figure will grow to $6.335 billion. With the development of 5G and artificial intelligence, it is expected that by 2025, the scale of FPGAs will reach about 12.521 billion US dollars. On the one hand, chip manufacturers need to rely on FPGAs for simulation and prototyping; on the other hand, CPUs, GPUs, FPGAs, and ASICs (application-specific integrated circuits) are increasingly competing in the AI market. In the global fpga market, Xilinx and altera have a market share of about 90%. Sales revenue was US$850 million, an increase of 24% over the same period last year; net profit was US$241 million, an increase of 27% over the same period last year.

We use the example of fast corners to illustrate the process of implementing OpenCV with VivadoHLS. Finally, the functions in the rewritten OpenCV design are replaced with video functions of the corresponding functions provided by HLS, and synthesized using VivadoHLS, implemented in FPGA programmable logic or as a Zynq SoC hardware accelerator under the Xilinx development environment. Next, establish the OpenCV processing algorithm based on the video data stream chain, and rewrite the usual design of the previous OpenCV. This rewrite is to be the same as the HLS video library processing mechanism, which is convenient for the function replacement in the following steps. Of course, these synthesizable codes can also run on a processor or ARM. First, develop an OpenCV-based fast corner algorithm design and validate this algorithm using OpenCV-based test-inspired simulations.