XC7K70T-2FBG484I_XC7Z100-2FF900E Introduction

This year, it has successively released the integrated SmartNIC platform AlveoU25, the strongest 7nm cloud chip Versal Premium, and an innovative TCON (Timing Controller, timing controller) solution for FPGA devices. As an FPGA (Field Programmable Gate Array)-based company, Xilinx's strategy lies in three aspects: "data center priority", "accelerating the development of the core market" and "driving adaptive computing".

Today, there is a lot of breaking news about AMD. Excellent performance and excellent specifications let consumers once again call out: AMD YES!. First of all, AMD officially announced the new Zen 3 CPU architecture and brought the latest generation of Ryzen 5000 series desktop processors.

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Like the outside world's neutral view of Arm, once AMD successfully acquires Xilinx, downstream customers will only have two choices when purchasing FPGA chips and related solutions, which will increase the concerns of downstream companies. Xilinx once revealed to the media that because Intel acquired Altera, many potential customers will hand over more orders to Xilinx for the sake of neutrality, so Xilinx's share in the FPGA market has increased significantly in the past two years. Some industry analysts pointed out that if AMD succeeds in winning Xilinx, it will bring a new competitive landscape to the global semiconductor industry.

The AI engine is a highly optimized processor that includes the following key features: 32-bit scalar RISC processor (named Scalar Unit) 1 x 512b SIMD vector unit (vector fixed-point/integer unit available) and 1 single-precision floating-point (SPFP) ) Vector Unit 3 Address Generator Units (AGU) Very Long Instruction Word (VLIW) Function 3 Data Memory Ports (2 Load Ports, 1 Store Port) Direct Streaming Interface (2 Input Streams, 2 Output Streams) ).

Compared with the i5-10600K, the Ryzen 5 5600X is 19% higher in single thread, 20% higher in multi-threading, and 13% higher in 1080p gaming performance. Judging from the official comparison data, the new generation of Ryzen 5000 series processors is much stronger than the tenth-generation products of competitors: Ryzen 9 5900X is 13% higher than i9-10900K in single thread and 23% higher in multi-thread. %, 3% better gaming performance at 1080p. Compared with the i7-10700K, the Ryzen 7 5800X is 9% higher in single thread, 11% higher in multi-thread, and the 1080p game performance is the same. Among them, the Ryzen 9 5900X processor has been praised by AMD as "the best gaming CPU in the world" - this title has always been in the hands of Intel. The brand new architecture, the strongest game processor should come, and so on, the party has not waited in vain.

It will also describe the bidirectional data transfer between the AI engine array and other ACAP devices (PL or DDR). Xilinx will provide a C++ framework to create Graphs from the kernel. In order to fully grasp the kernel location, there will be a series of methods available to constrain the layout (kernels, caches, system memory, etc.). These nodes can be contained within an AI engine array or within programmable logic (HLS cores). The Graph will instantiate and wire the kernels together using caches and data streams. This frame contains Graph nodes and connection declarations.

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Interestingly, it can be seen that the AXI4 memory-mapped direct communication channel exists only between the NoC to the AI engine tile, but not from the AI engine tile to the NoC.

First, develop an OpenCV-based fast corner algorithm design and validate this algorithm using OpenCV-based test-inspired simulations. Of course, these synthesizable codes can also run on a processor or ARM. Finally, the functions in the rewritten OpenCV design are replaced with video functions of the corresponding functions provided by HLS, and synthesized using VivadoHLS, implemented in FPGA programmable logic or as a Zynq SoC hardware accelerator under the Xilinx development environment. Next, establish the OpenCV processing algorithm based on the video data stream chain, and rewrite the usual design of the previous OpenCV. This rewrite is to be the same as the HLS video library processing mechanism, which is convenient for the function replacement in the following steps. We use the example of fast corners to illustrate the process of implementing OpenCV with VivadoHLS.