XC7K70T-2FBG676C_XC7Z100-2FF900I Introduction

In the data center space, it is important to realize that Xilinx can support not only compute acceleration and data center applications, but also value-creating storage and networking. In order to better adapt to the new world of intelligent interconnection, Xilinx continues to take "flexible platform" as the core of its products, seizes new industrial opportunities, and formulates three major development strategies to support wider market applications. Victor Peng pointed out that the first strategy is "data center first."

The accelerated computing of CPU+GPU+FPGA is undoubtedly aimed at the blue ocean of the data center field. Intel has repeatedly stated that it is a data-centric company, while NVIDIA has recently proposed acquisitions and released various The determination to "take the high ground" is constantly revealed in new products….

XC7K70T-2FBG676C_XC7Z100-2FF900I

XC7K70T-3FBG676E

But in recent years, AMD's data center processor business has been growing, and the competition with Intel, which has long dominated the field, has become increasingly fierce. The addition of Xilinx will put AMD in a better position to compete with Intel. , and capture a larger share of the fast-growing telecom and defense markets. .

Like the outside world's neutral view of Arm, once AMD successfully acquires Xilinx, downstream customers will only have two choices when purchasing FPGA chips and related solutions, which will increase the concerns of downstream companies. Xilinx once revealed to the media that because Intel acquired Altera, many potential customers will hand over more orders to Xilinx for the sake of neutrality, so Xilinx's share in the FPGA market has increased significantly in the past two years. Some industry analysts pointed out that if AMD succeeds in winning Xilinx, it will bring a new competitive landscape to the global semiconductor industry.

It will also describe the bidirectional data transfer between the AI engine array and other ACAP devices (PL or DDR). Xilinx will provide a C++ framework to create Graphs from the kernel. In order to fully grasp the kernel location, there will be a series of methods available to constrain the layout (kernels, caches, system memory, etc.). These nodes can be contained within an AI engine array or within programmable logic (HLS cores). The Graph will instantiate and wire the kernels together using caches and data streams. This frame contains Graph nodes and connection declarations.

The AI engine is a highly optimized processor that includes the following key features: 32-bit scalar RISC processor (named Scalar Unit) 1 x 512b SIMD vector unit (vector fixed-point/integer unit available) and 1 single-precision floating-point (SPFP) ) Vector Unit 3 Address Generator Units (AGU) Very Long Instruction Word (VLIW) Function 3 Data Memory Ports (2 Load Ports, 1 Store Port) Direct Streaming Interface (2 Input Streams, 2 Output Streams) ).

XC7K70T-2FBG676C_XC7Z100-2FF900I

XC7Z045-L2FFG676E

XCV2004FG456C XCV200-4FG456 XCV200-4FG256I XCV200-4FG256C XCV2004FG256C XCV200-4FG256 XCV200-4BGG352I XCV200-4BGG352C XCV200-4BGG256I XCV200-4BGG256C XCV200-4BG432C XCV200-4BG356C XCV200-4BG352I XCV200-4BG352C XCV200-4BG256I XCV200-4BG256C XCV200-4BG256 。

XCS30XLVQ100AKP XCS30XLVQ100-4I XCS30XLVQ100-4C XCS30XL-VQ100 XCS30XLTQ144AKP-4I XCS30XLTQ144AKP0645 XCS30XL-TQ144AKP XCS30XLTQ144AKP XCS30XLTQ144AK-4I XCS30XLTQ144A XCS30XLTQ144-4C XCS30XL-TQ144 XCS30XLTMPQ208AKP XCS30XLtm-4PQ240C XCS30XLTM-4ITQ144AKP 。

XQ4VFX60-10EF672M X04VF100-11F152I XQ4VFX140-10FF1517I XQ4VLX60-10FFG1148M XQ4YLX60-10FF668M XQ4VSX35-9F668I XQ4VLX25-11SF363M XQ4VLX25-SFG363 XQ4VLX25-10FF668I XQ4YFX60-10EF672M XQ4VLX25-10SFG363M XQ4VLX25-10F68I XQ4VLX60-10FF68M XQ4VK60-10FF1148M XQ4VLX160-10FF148I 。

XQ6VLX130T-1RF1156M XQ6VLX240T-1RF1759M XQ6VLX550T-L1RF1759I XQ6VSX315T-L1FFG1156I XQ6VLX240T-2RF1759I XQ6VLX240T-1RF1156M XQ6VLX240T-2FFG1156I XQ6VLX130T-1FFG1156M XQ6VLX130T-2FFG1156I XQ6VLX130T-1RF784I XQ6VLX130T-1FFG1156I. XQ6VLX240T-1RF784M XQ6VLX240T-2RF1156I. 。

XC7K70T-2FBG676C_XC7Z100-2FF900I

Interestingly, it can be seen that the AXI4 memory-mapped direct communication channel exists only between the NoC to the AI engine tile, but not from the AI engine tile to the NoC.

The VivadoHLS video processing library uses the hls::Mat<> data type, which is used to model the processing of video pixel streams, and is essentially equivalent to the hls::steam<> stream type, rather than stored in external memory in OpenCV. matrix matrix type. Therefore, in the design of OpenCV with VivadoHLS, it is necessary to modify the input and output HLS synthesizable video design interface to the Video stream interface, that is, use the video interface provided by HLS to synthesize the function to realize AXI4 video stream to VivadoHLS in hls ::Mat<> type conversion.