XC6VLX365T-3FF1759C_XC4VLX200-11FF1513I Introduction

As an FPGA (Field Programmable Gate Array)-based company, Xilinx's strategy lies in three aspects: "data center priority", "accelerating the development of the core market" and "driving adaptive computing". This year, it has successively released the integrated SmartNIC platform AlveoU25, the strongest 7nm cloud chip Versal Premium, and an innovative TCON (Timing Controller, timing controller) solution for FPGA devices.

On the other hand, AMD and Xilinx have been working closely together for a long time. A series of storage system-oriented IPs such as NVMe HA, NVMe TC and Embedded RDMA previously provided for AMD EPYC (Xiaolong) data center processors can help AMD build low latency The high-efficiency data path, thus realizing the efficient storage acceleration function of FPGA. In fact, a similar plot was staged as early as 2015, when Intel (Intel) acquired FPGA manufacturer Altera for $16.7 billion, and Altera also followed the trend for Intel's follow-up "CPU+xPU (GPU+FPGA+ASIC+ eASIC)” strategy provides the most solid foundation.

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Compared to the previous platform, the system-level performance per power has been improved by 4 times. It supports Xilinx Vitis AI, which provides extensive capabilities for building AI inference using accelerated libraries. In addition, it provides excellent high-level synthesis (HLS) capabilities. Softnautics selected the Xilinx Ultrascale+ platform because it offers the best in application processing and FPGA acceleration.

A variety of power-driven design techniques are used in the design of FPGAs. Taking the Xilinx Virtex series as an example, because the configuration memory cells can occupy 1/3 of the number of transistors in the FPGA, a low leakage current "midox" transistor is used in this series to reduce the leakage current of the memory cells. The power consumption of the multipliers in the DSP block is less than 20% of the power consumption of the multipliers built in the FPGA fabric. Given the wide range of leakage current distributions that can result from manufacturing variations, low leakage current devices can be screened to effectively provide devices with core leakage power consumption below 60%. The dynamic power problem is solved with low-capacitance circuits and custom modules. To reduce static power dissipation, longer-channel and higher-threshold transistors are also used across the board.

The prevailing view is that this requirement cannot be met by CPUs alone, and that some form of computational acceleration is needed to handle AI inference workloads more efficiently. However, with opportunities come challenges. AI inference, the process of using trained machine learning algorithms to make predictions, whether deployed in the cloud, edge, or on-device, requires excellent processing performance within a tight power budget.

Plus case (uppercase/lowercase/full small/small case), italic (Italian/Roman), scale (horizontal scale), weight, specified size (display/text), squiggly, serif (Generally divided into serifs and sans-serifs), this number can scale to millions, making text recognition an exciting professional discipline in the field of machine learning. As human language writing forms have evolved, thousands of unique character systems have developed. .

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Elevated temperature can cause an exponential rise in leakage power dissipation. For example, increasing the temperature from 85°C to 100°C can increase leakage power consumption by 25%. As shown in Figure 1, power dissipation is highly dependent on supply voltage and temperature. Reducing the FPGA supply voltage results in a quadratic decrease in dynamic power and an exponential decrease in leakage power.

Let's analyze the decomposition of the total power consumption of the FPGA in order to understand the main power consumption. Taking Xilinx Spartan-3 XC3S1000 FPGA as an example, assume that the clock frequency is 100MHz, the inversion rate is 12.5%, and the resource utilization rate is the typical value of various actual design benchmarks. FPGA power consumption is design-dependent, that is, depends on device family, clock frequency, toggle rate, and resource utilization.