application

motor control

illustrate

The ADS7869 is a motor control front end that includes three analog-to-digital converters (ADCs) with a total of seven sample-and-hold capacitors and 12 fully differential input channels. There are four sign comparators connected to the four input channels. There are also three fully differential inputs; each input is connected to a window comparator and a sign comparator.

In addition, the ADS7868 provides a very flexible digital interface with a parallel port that can be configured for different standards. In addition, a Serial Peripheral Interface (SPI) and a dedicated serial interface with three data lines ( VECANA01 mode) are provided. This allows the ADS7869 to interface with most digital signal processors (DSPs) or microcontrollers. This chip is dedicated to motor control applications. For position sensor analysis, two up and down counters are added to the silicon. This function ensures that the analog input of the encoder is kept at the same point in time as the counter value.

Typical Application Circuit

Figure 1-1 shows an example of a typical motor control circuit. The IU, IV and IW channels measure the current of the motor. The position (speed) and load of the motor are simultaneously measured by A1, B1 and A2, B2 using resolver or analog encoder sensors, respectively. Asynchronous inputs AX and BX can be used to capture the encoder's reference signal for absolute position. Channel AN1 measures the differential DC link voltage. AN3 measures the temperature of the motor. The auxiliary voltage can be measured with channel AN2. The counter inputs are connected to the appropriate comparator outputs (A1 to CNTA1, B1 to CNTB1, etc.). The level input DAIN of the window comparator should be connected to the 8-bit DAC output DAOUT.

analog segment

The analog section handles the analog-to-digital converter, including gain and offset adjustments. Also discussed are analog inputs, seven-symbol comparators, three-window comparators, 8-bit digital-to-analog converters (DACs), reference voltages, ground, and supply voltages.

Fully differential analog input

A/D converter input

The 12 inputs of the adc and the 3 inputs of the comparator (U_C, V_C, and W_C) are fully differential, providing good common-mode rejection of 60dB at 50kHz. This is important for noise suppression in harsh environments.

The seven sample-and-hold circuits from the ADC contain a 5pF capacitor (C in Figure 1-3) connected to the analog input through a switch. Turn on the switch to save the data. After the conversion is complete, the switch is closed. The capacitor is then loaded to an initial voltage that is equal to the reference voltage at the ADC, which is selected by gain adjustment.

When the input switch is closed, the voltage at the input pin is usually different from the voltage on the sample capacitor. The sample capacitor needs to be charged to 12-bit accuracy, or half the least significant bit (LSB), within an acquisition time (t) of at least 200ns. Inverse quotient

The minimum -3dB bandwidth to drive an op amp can be calculated as:

When n is equal to 12, the resolution of the ADC (for the ADS7869). When t=200ns, the minimum bandwidth of the driver amplifier is 7MHz. If the application increases the acquisition time, the bandwidth can be relaxed.

The OPA364 from Texas Instruments is recommended; in addition to the necessary bandwidth, it provides low offset in a small package at a low price.

The phase margin of the driving op amp is usually reduced by the sampling capacitor of the ADC. The resistance between the capacitor and the amplifier reduces this effect; therefore, the internal 300Ω resistor (RSER) is in series with the switch. The resistance of the closed switch (RSW) is about 80Ω. See Figure 1-3.

The differential input range of the ADC (positive and negative inputs) is ±REF_ADC, the reference for the converter, selected by gain adjustment.

It is important that the voltage on all inputs must not exceed 0.3V above the analog supply or 0.3V below ground. There is no DC current at the input. Current is only required to charge the sample and hold capacitors.

window comparator input

A sampling structure was chosen for the window comparator. The sampling time is two clock cycles and the minimum t (see Equation 1) is 125ns. The necessary accuracy is 10mV (see the 8-bit DAC section), and the input range is 5V. The required bandwidth of the driver amplifier is 8.8MHz (see Equation 1). OPAx354 from Texas Instruments is recommended.

The input circuit of the window comparator is similar to the ADC input. The only difference is that the sampling capacitor is reduced to 2.5pF. (See Figures 1-4.)

Sign Comparator Input

Four sign comparators are connected to the ADC inputs (A1, B1, A2, and B2); three sign comparators are connected to the window comparator inputs (U_C, V_C, and W_C).

The sampling capacitors of the adc and window comparators can generate voltage glitches, so it is important to drive low impedance inputs.

The lower voltage of the differential input should be kept in the range of 0 to AV−1.8V.

analog to digital converter

The ADS7869 includes three SAR-type 1MSP, 12-bit ADCs, and three pairs of S/H capacitors, which are connected to ADC1 and ADC2, respectively. A single S/H capacitor is connected to ADC3. Gain and offset adjustments are added to each ADC. (

keep 1, keep 2

When the HOLDx signal goes low, the analog input remains unchanged. Synchronizer's charge sample and hold (S/H) freeze on the falling edge of hold 1. The setup time for HOLD1 is typically 25ns relative to the rising edge of the system clock. Conversion will start automatically on the next rising edge of the clock. After the conversion is completed, the S/H switches back to the sampling mode, 1-5 cycles after 12 clocks. This point in time is represented by DAV. (See Figure 1-10 on page 26.) After a conversion begins, HOLD1 must go high at the latest on the 13th falling clock.

Asynchronous sample and hold (S/H) is triggered by an active low hold 2 signal. Set the time to 0 ns for 6-7 brackets 2 next to the falling edge of bracket 1; see Figure 1-10. When these S/H circuits are selected through the digital interface and the HOLD1 signal goes low, the conversion of these S/H circuits is initiated. When the HOLD2 signal goes high, the input is connected back to the S/H capacitor. HOLD2 needs to be low during the entire conversion process. Cage 1 and Cage 2 can be connected together.

clock

The ADC uses an external clock CLK, which needs to be in the range of 1MHz to 16MHz. Conversion requires 12 clock cycles and acquisition requires at least 4 clock cycles. Therefore, the maximum throughput of 1MSPs is achieved with a 16MHz clock and 16 clock cycles per full conversion cycle. The duty cycle should be 50%; however, the ADS7869 will still function properly with a duty cycle between 30% and 70%.

reset

The reset condition stops any ongoing conversions and reconnects the sync S/Hs to the input; see the reset section.

Gain adjustment

The output of the 12-bit DAC (REF_ADC) is used as the reference voltage for the ADC. There is one DAC per ADC. The voltage range is between 0V (code 000H) and REFIN (code FFFH) at 2.5V. If the selected voltage is in the range of 0.5V to 2.5V, the ADC is working fine. The output voltage of the DAC sets the differential input range of the ADC, which is ±REF_ADC. The desired input range can be adjusted in 1.22mV steps.

In VECANA mode, the gain information contained in the digital input word ADIN automatically sets the DAC value. See the Vecana interface section for more information.

In all other modes, each input channel within the digital interface has a register that stores gain information for any given channel. When the application selects a specific channel, the value of this register is automatically written to the DAC, and the DAC output is adjusted to the desired value. The DAC settles to this value within 250 ns (equivalent to the minimum acquisition time).

When a reset condition occurs, the gain information in the register is set to zero. These registers need to be set to selected values before using the ADC.

In VECANA mode, the DAC is initially set to full scale with a differential input range equal to ±(voltage at the REFIN pin).

Note: A fundamental offset error occurs when data is held on sampling capacitors A2 and B2 (or AX and BX) and the ADC's gain is modified in an intermediate conversion before converting a particular channel A2 and B2 (or AX and BX). This offset error is possible in two cases:

1. Data can be stored on asynchronous sample and hold capacitors AX and BX through the HOLD2 signal. Other channels can be switched before asynchronous signals AX and BX. Offset errors occur if the gain changes during these transitions.

2. Using input commands 4-6, channels A1 and B1 are kept together with A2 and B2. Channels A1 and B1 will be converted first. During this transition or further intermediate transitions, an offset error occurs if the gain is modified prior to the transition of channels A2 and B2.

offset adjustment

Similar to gain, offset can be adjusted to a 12-bit level relative to the ADC's actual input voltage range. For example, if the input range is ±1V, the offset can be adjusted in 488×V increments up to ±12.5% of the input range.

There is a register within the digital interface for each input channel. This register stores the offset adjustment value for each channel. When you select the channel to convert, the offset is automatically adjusted. During the conversion process, the selected channel and associated register information must not be changed.

Setting the register to 201H results in a -12.5% adjustment, 000H results in no adjustment, and 1fh results in a +12.5% adjustment. Offset adjustment value 200H is not allowed.

Offset adjustment cannot be used in VECANA mode. Resetting the condition sets the offset adjustment to zero.

transition noise

The transition noise of the ADS7869 itself is very low, as shown in Figure 1-5. This histogram was generated by applying a low noise DC input and starting 8000 conversions.

symbol comparator

The ADS7869 includes two sets of sign comparators with different hysteresis. The first group is used for position sensor inputs in motor control applications and is connected to inputs A1, B1, A2 and B2. The hysteresis of these comparators is typically 75mV. In motor control applications, these comparators are used to measure the sign of the position sensor input signal.

The second group is connected in parallel with the window comparators at the UC;, VC; and WC pins. The hysteresis of these components is typically 10 mV. In motor control applications, these comparators are used to measure the sign of the mains current.

If the differential input voltage is higher than +1/2 of the hysteresis, the sign comparator switches from 0 to 1. If the output is 1, the sign comparator switches back to 0 if the differential input voltage is below -1/2 of the hysteresis. See Figures 1-6.

The input range of the comparator is limited. The lower voltage of the differential input should always be in the range of 0 to AV−1.8V.

On each comparator, the output is delayed to the input voltage. This delay depends on the overdrive of the comparator input. Overdrive is the input voltage (VIN) minus half the hysteresis.

If the differential input voltage of the position sensor sign comparator switches from -40 mV to +40 mV (step function, 2.5 mV overdrive), the delay time of the output is typically 100 ns. If the comparator switches between -100mV and +100mV (72.5mV overdrive), the delay is typically reduced to 25ns. See Figure 1-7 and Figure 1-8 for the delay time as a function of step size for different overdrive gears.

window comparator

The window comparator tests whether the input voltage is within a certain range; the range is ±(voltage applied to DAN, pin 30). If the differential input voltage remains within this range, the output of the window comparator is 1. If the voltage is outside this range, the output is set to 0. The window comparator has a hysteresis that is turned on when the output is 0. When the input voltage is within ±(DAIN-60mV), the comparator output switches back to 1. (See Figure 1-9.) The voltage at DAIN needs to be in the range of 0.5V to 2.5V.

The window comparator has a switched capacitor circuit, similar to the ADC structure, but is different from other window comparators. This design greatly improves accuracy; due to the extra accuracy, a proper input signal front end is required. (See the Window Comparator Inputs section.)

Two clock cycles are used to sample the input. The next two clock cycles are used to test the lower and upper voltage limits. The output of the window comparator is updated every four clock cycles (or every 250ns for a 16MHz clock). In the worst case, the window comparator needs six clock cycles to detect the current limit. The window comparator requires a continuous clock to function properly.

In motor control applications, window comparators are used to monitor mains current for faults.

digital to analog converter

DAIN (pin 30) requires a voltage between 0.5V and 2.5V to set the range of the window comparator; this can be achieved with an 8-bit DAC. The DAC value is programmed through the digital interface.

00H corresponds to a DAC output voltage of 0V. The full-scale value (FFH) is 2.49V (internal reference minus 1LSB).

The output impedance is typically 10kΩ; the output impedance is independent of the output voltage. The DAC output is connected to DAOUT (pin 29). The settling time (t) depends on the external capacitor (C) on this pin and can be calculated as:

In this equation, n equals 8, the resolution of the DAC. The output impedance also limits the output current. This current should not exceed 0.5µA (0.5µA 10kΩ=5mV).

Dout and Dan can go short. A capacitor (typically 0.1µF) can be used for the low-pass DAC output; however, this low-pass configuration is not required.

internal reference

The internal reference REFOUT (Pin 96) provides the 2.5V required by the ADC reference input at REFIN (Pin 97). An internal buffer with a high impedance output drives the reference output pin. This internal buffer is optimized to troubleshoot faults at the reference pins. Either capacitor can be connected to the reset pin to reduce noise. It is recommended to connect a 0.1µF capacitor between REOUT (Pin 96) and SGND (Pin 13). Signal ground SGND is used internally as a negative reference. The reference voltage is considered to be the differential voltage between this ground and the re-output.

Normally, both the REFOUT and REFIN pins are shorted. The internal reference provides good temperature drift, typically 20ppm, with an initial accuracy of 2.5V±20mV at 25°C. If this does not provide the accuracy required by the application, an external reference can be connected to the REFIN pin.

ground

The best test results were achieved on a solid ground: linearity, offset and noise performance all showed improvements. During PCB layout, care should be taken that loop currents do not pass through any sensitive areas or signals.

Digital signals interfaced with the ADS7869 are referenced to a solid ground plane. The ESD protection diodes inside the ADS7869 begin to conduct when ground is separated and the digital input is below -0.3V; this includes short-circuit faults. Current will flow through the substrate of the ADS7869 and interfere with the analog performance.

supply

The ADS7869 has two independent power supplies, BV (pins 48 and 78) and AV (pins 8, 18, 28, 85 and 98).

The BV is only used as a numeric keypad power supply and has a voltage range of 2.7V to 5.5V. This enables the ADS7869 to interface with all state-of-the-art processors and controllers. To limit the noise energy from external digital circuits to the ADS7869, BV must be filtered. The current through BV is well below 5mA; depending on the external load, a 10Ω to 100Ω resistor can be placed between the external digital circuit and the ADS7869. Bypass capacitors (two 0.1µF and one 10µF) should be placed between the two BVDD pins and the ground plane.

The AV powers the internal circuits, ranging from 4.5 volts to 5.5 volts. Since the supply current of the ADS7869 is typically 45 mA, it is not possible to use a passive filter between the application's digital board power supply and the AV pins. To generate the analog supply voltage for the ADS7869 and the necessary analog front end, a linear regulator (7805 series) is recommended. A 0.1µF bypass capacitor should be placed between all AV pins and the ground plane. A 10µF bypass capacitor should be placed between the two AV pins and the ground plane.

digital part

Introduction

The ADS7869 can interface with a DSP or μC in four different ways. The M1 and M0 pins determine in which mode the ADS7869 will communicate; see Table 1-1. It can be connected as a standard VECANA01 interface, SPI or two different parallel interfaces.

As a function of the selected mode, some pins will have different assignments, as shown in Table 1-2. Table 1-2.

(1), NC means no connection. The NC pin in VECANA01 and SPI mode should use a pull-down resistor to ground.

(2) For parallel mode 11, there is a sub-mode compatible with the TMS320c54xx DSP series; see the section on Mode 11 bus access (TMS320c54xx DSP series compatibility mode).

(3), the original VECANA01 pin name.

VECANA interface

The VECANA01 mode of the ADS7869 interface is exactly the same as the original VECANA01 interface. This mode was added to the ADS7869 for backward compatibility. The VECANA01 interface is a dedicated serial interface with one serial input and three serial outputs.

Sampling and conversion are controlled by the HOLD1 and CLK inputs. The ADS7869 is designed to operate with an external clock provided at the CLK input. This allows conversions to be synchronized with the system clock, reducing transient noise effects. The DAV signal indicates when a transition occurs with a low-level pulse. The DAV signal is equivalent to the ADBUSY signal in VECANA01.

The typical clock frequency for the specified accuracy is 16MHz. This will result in a full conversion cycle with S/H acquisition and a 1 µs analog-to-digital (A/D) conversion cycle and start again at the beginning of the next conversion (after HOLD1 goes low); see the WINCLK selection section.

When the ADS7869 is powered up, initialization requires one conversion cycle before valid digital data is transferred on the second cycle. The first conversion after power-up is performed with indeterminate configuration values in the input setup registers. The second transformation uses these values to perform the correct transformation and output valid numeric data from each adc.

The setup word received by the ADS7869 is used for the next conversion cycle, while the adc converts and transmits its serial digital data in one conversion cycle. The 13-bit word is supplied to ADIN (pin 67) and stored in the buffered input setup register.

The configuration parameters are: DAC output voltage; programmable gain/input voltage range; input multiplexer; and sample and hold selection.

The DAC input portion of the ADI word (bits DAC[7…0]) determines the value of the DAC output voltage; see Table 1-5. The 8-bit DAC has 256 possible output steps, from 0V to +2.490V. The value of 1LSB is 9.76mV (see Table 1-3 for input/output relationship).

Table 1-3 through Table 1-6 show information about these parameters.

The gain selection section (bit gain[1..0]) determines the programmable gain of the ADIN word; see Table 1-5. The gain of all three ADCs is set by a gain input parameter. The gain values and allowable full-scale inputs are shown in Table 1-4.

The gain settings and input voltage range for channels AN1, AN2, and AN3 at ADC3 are always 1.0V/V relative to ±2.5V.

Input channel selection

Table 1-6 shows the relationship between the value of the input select bits and the input channel being converted.

input select=0H

Synchronize sample and hold, SH, sample AN3 (only), then ADC3 converts it on signal hold 1. Input selection = 1H5, AX is sampled by asynchronous sample and hold SH6 and signal hold 2; ADC1 is on, signal hold 1. BX is sampled by asynchronous sample and hold SH7 and signal hold 2; ADC2 converts it on signal hold 1. AN3 is sampled and held synchronously, SH5 then ADC3 converts it on signal hold 1.

During the entire conversion process, the signal must remain 2 low. If 2 is held high before conversion begins, ADC1 and ADC2 will not convert.

input_select=2H

A2 is sampled by synchronous sample and hold SH; ADC1 converts it on signal hold 1. B2 is sampled by synchronous sample and hold SH; ADC2 converts it on signal hold 1. AN2 is sampled by synchronous sample and hold SH; ADC3 converts it on signal hold 1.

input_select=3H

A2 is converted by ADC1 on signal holder 1. A2 selects 4H, 5H, or 6H to upsample on SH in the previous conversion of the input. B2 on signal holder 1 is converted by ADC2. In the previous conversion, B2 was sampled on SH, and the input selected 4H, 5H, or 6H. AN2 is converted on signal holder 1 by synchronous sample and hold (SH; ADC3) sampling.

Input selection = 4H, 5H and 6H

A1 is sampled by synchronous sample and hold SH; ADC1 converts it on signal hold 1. B1 is sampled by synchronous sample and hold SH; ADC2 converts it on signal hold 1. AN1 is sampled by synchronous sample and hold SH; ADC3 converts it on signal hold 1. A2 is sampled and held by synchronous, SH, the signal is held at 1. B2 is sampled and held by synchronous, SH4 on the signal holder 1.

input selection=7H

IU is sampled by synchronous sample and hold SH; ADC1 converts it on signal hold 1. IV is sampled by synchronous sample and hold SH; ADC2 converts it on signal hold 1. IW is sampled by synchronous sample and hold SH; ADC3 converts it on signal hold 1.

VECANA timing characteristics (1)

Exceeds the recommended operating free air temperature range of -40°C to +85°C, Avg=5V, BV=3V−5V.

WINCLK selection

In VECANA01 mode, a separate clock can be applied for the window comparator on WINCLK (pin 51). By using pins S0 (pin 52) and S1 (pin 53) as decoder inputs, the window comparator can be supplied with the system clock, an external clock (provided by WINCLK), and two separate external clocks.

The system clock provided by CLK (pin 77) drives the window comparator in other modes (SPI and parallel).

The window comparator clock WINCLK must be synchronized with the system clock provided by CLK (pin 77). When the system is running at a 15MHz clock, a 6MHz clock can be provided to the window comparator.

In order to provide a maximum window comparator with 1µs detection time, a minimum clock of 6MHz must be provided. See the Window Comparator section. The window comparator must be operated with a continuous clock.

Serial Peripheral Interface (SPI)

The SPI runs completely asynchronously with the rest of the system. The four signals of SPI are SPICLK, SPISIMO, and the maximum speed of SPI is 25MHz. When the select signal SPISTE is high, the entire SPI is in a reset state except for the address and data registers. SPI clock SPICLK and serial When SPISTE is high, the data input SPISIMO is disabled. Incoming data is triggered by the SPI on the falling edge of SPICLK. The output data is placed on output SPISOMI on the rising edge of SPICLK (see Figure 1-11). For the transfer of a 16-bit data word, 24 bits are required. The first input bit of the ADS7869 determines whether the entire transfer is a read or write operation. "1" means read and "0" means write operation. There are seven address bits, but only six lsbs are used. Then send or receive 16 data bits.

Complete a 16-bit transfer as follows:

1. On the first falling edge of SPICLK, the read/write bit is stroked.

2. On the third falling edge of SPICLK, the MSB of the address (bit 5) is strobed.

3. On the eighth falling edge of SPICLK, the LSB of the address (bit 0) is strobed and the corresponding data from the register map is read.

4. On the ninth rising edge, the data read from the register map is latched into the shift register and shifted by one position on each rising edge of SPICLK. This data is always sent even if a write operation is performed.

5. On the 24th falling edge of SPICLK, if a write operation is performed, the last data bit is shifted in from SPISIMO and a write pulse is generated to write the data to the register map.

During consecutive reads or writes (see Figure 1-12), the address is decremented after each read or write; see the indicator arrows. When the address is set to 00H, at the beginning, the FIFO can be read out quickly. This data is written to the register map on the 16th SPICLK of the data word. If SPISTE is inactive before the 16th SPICLK in the data word, data is not written to the register map; therefore, data is lost.

Timing Characteristics

Exceeds the recommended operating free air temperature range of -40°C to +85°C, Avg=5V, BV=3V−5V.

Parallel interface

The parallel interface has the following main functions:

1. Data words:

(1) A data path with a width of 16 bits is supported.

2. Bus handshake:

(1), separate RD and WR type control signals.

(2) Separate R/W and WE control signals.

3. Mapping

(1) The ADS7869 is shown as a memory-mapped peripheral.

(2) The internal registers are directly mapped to consecutive locations in the external bus address space.

Parallel read and write control

Reading and writing from the ADS7869 is controlled by the chip select input (CS, pin 57), the write input (WR, pin 58) and the read input (RD, pin 59). Mode 11 has a control bit that can be reset to activate a special compatibility mode. (See the Mode 11 Bus Access [DSP Compatible Modes] section.) Depending on the host processor's needs, the read/write pins can be configured for combined read/write and write enable. Mode pins M0 and M1 determine how the host accesses the ADS7869.

Mode 10 bus access

When M1=1 and M0=0 (mode 10), the host port uses RD (pin 59) as the read/write signal (R/W) and WR (pin 58) as the write enable signal WE. The current cycle is processed only when the chip select input CS (pin 57) of the ADS7869 is active low.

R/W determines the direction of transfers within a bus cycle; see Figure 1-14. When R/W is high, data is placed on the database by the ADS7869, according to the address, as long as CS is low.

For a write cycle, a low signal (on WE) indicates to the ADS7869 that data on the bus is valid. The rising edge of AND data is latched in the ADS7869. A valid access to the ADS7869 is detected when the host sets CS low (see Figure 1-15).

Read Timing Characteristics

Exceeds the recommended operating free air temperature range of -40°C to +85°C, Avg=5V, BV=3V−5V.

Mode 11 bus access (standard mode)

When M1=1 and M0=1 (mode 11), the host port uses WR (pin 58) and RD (pin 59) for independent read and write access to the ADS7869. The current cycle is processed only when the CS (pin 57) input of the ADS7869 is active low. Bit 0 of the parallel register (address 27h) must have a reset value of 1 to use standard mode.

In Mode 11 operation, the RD indicates to the ADS7869 that the host processor has requested a data transfer (see Figure 1-16). The ADS7869 outputs data to the host. Addresses can be changed during CS low cycles and multiple data can be read.

To configure the registers in the ADS7869, the host issues a WR signal to indicate that valid data is available

on the bus. With the rising edge of WR, data is latched into the ADS7869; see Figure 1-17. address because the ADS7869 must be valid before a write operation can occur. The CS signal can be held low between two consecutive writes.

Mode 11 bus access (TMS320c54xx DSP family compatible mode)

In the TMS320c54xx DSP family compatibility mode (M1=1 and M0=1), the host port uses CS (pin 57) along with WR (pin 57) as R/W for independent read and write access to the ADS7869. Bit 0 of the parallel register (address 27) must have a value of 0 to use this compatibility mode.

In this mode, CS, together with R/W (held high), indicates to the ADS7869 that the host processor has requested a read data transfer (see Figure 1-18). The ADS7869 outputs data to the host as long as CS is active low.

To configure the registers, in the ADS7869, the master sets the R/W signal low to indicate that valid data is available on the bus. With the rising edge of CS, data is latched into the ADS7869 (see Figure 1-19). The address of the ADS7869 must be valid before CS is set low.

Register bit 0 at address 27H must be reset before using this mode. Since the write access is similar to that of Mode 11, a reset can be performed using the original Mode 11 TMS320C54xx DSP write operation. (See the Mode 11 Bus Access [Standard Mode] section.) This mode can perform a read operation after resetting bit 0, as described above.

FIFO data register (00H)

The FIFO data register is located at address 00H in the register map. The output word of the FIFO is in 16-bit format. The resolution of the ADC is 12 bits. The output data of each adc is in binary 2's complement format. Four msb are used for channel identification.

Each conversion has three words stored in the FIFO. Three read accesses to this register are required to obtain all three conversion values from the FIFO.

Offset Register (01H to 0CH)

The offset registers are stored at addresses 01H to 0CH. The offset register is 10 bits wide and is represented in two's complement format. The sign bit is copied to bit positions 15 to 10. This copying is performed by read access only (ie, bits 15 to 10 cannot be set correctly to achieve a copy of the sign bit). Valid offset adjustment values are from -511 (201H) to +511 (1fh). The value –512 (200H) is not allowed.

Gain Register (0DH to 18H)

Gain registers are stored at addresses 0DH to 18H. The gain register is 12 bits wide. Gain values are stored in straight binary format.

WINDAC register (19H)

The WINDAC register is located at address 19H. The WINDAC register sets the output of the 8-bit DAC used by the window comparator. The word is in straight binary format with 8 bits. The output voltage is a function of the register value and the internal reference voltage.

Control Register (1AH)

The control register is located at address 1AH. The control register contains input selection and DAV pin control. (See the FIFO section for more information.) The format of the control registers is shown in Table 1-16. See the Vecana Interfaces section for more information on input selection.

Counter Control/Status Register (1BH)

The Counter Control/Status Register is located at Address 1BH. The counter control/status register CCTRLSTAT is a combined control register for the filtered input of the counter, the status register for the overcurrent or undercurrent status of the counter and the filtered input signal triggered by HOLD1. See the Digital Counters section for more information on this topic.

When filter bits FxxE are set, the appropriate input is synchronized to the system clock and the digital filter processes the input signal. If the bit is reset, the signal is only synchronous.

The overflow state EOx/TOx is set when the appropriate counter reaches the value FFFFH. This means that the time between two edges of the input signal is greater than 4ms at 16MHz. Only the time counter keeps its value until a counter reset is performed. See the Reset Registers section for more information.

The filtered values of the counter inputs CNTA2, CNTA1, CNTB2, and CNTB1 are stored in the appropriate bits FB1, FA1, FB2, and FA2 with Sync Holder 1 and.

Edge count registers (1CH, 1DH, 20H and 21H)

The two edge counters have four shadow registers. Registers SYEDGCNT1 and SYEDGCNT2, Sync Edge Count 1 (Address 1DH) and Sync Edge Count 2 (Address 21H) lock the value from the edge counter when the Sync Hold Signal Hold 1 is set low.

The registers ASEDGCNT1, ASEDGCNT2, Asynchronous Edge Count 1 (in address 1CH) and Asynchronous Edge Count 2 (in Address 20H), hold the value from edge counter latch 2 set low on asynchronous hold signal.

Edge counter 1 EDGECNT1 is given an initial value by writing to register SYEDGCNT1. Edge counter 2 EDGECNT2 is supplied with an initial value by writing to register SYEDGCNT2.

Edge Period Registers (1EH and 22H)

The two edge period registers have two read-only shadow registers. Registers SYEDGPRD1 and SYEDGPRD2, Sync Edge Period 1 (Address 1EH) and Sync Edge Period 2 (Address 22H), when the Sync Hold Signal Hold 1 is set low, lock the value from the Edge Period register.

Edge time period registers (1FH and 23H)

The two edge time counters have two read-only shadow registers. Registers SYEDGTIME1 and SYEDGTIME2, Sync Edge Time 1 (Address 1FH) and Sync Edge Time 2 (Address 23H), when the Sync Hold Signal Hold 1 is set low, lock the value of the edge time counter.

FIFO test register (24 hours)

The purpose of the FIFO test register at address 24h is to test the FIFO during production testing; the FIFO fills the defined pattern through this register. The internal FIFO structure can be verified by reading the pattern of the FIFO data register. When the FIFO test is enabled, the multiplexer is switched and the data (of the FIFO test register) is introduced into the FIFO instead of normal ADC data; to simulate three ADCs, the data is latched into the FIFO three times. To differentiate the channels, the first data is unchanged to emulate ADC1, the second data is inverted to emulate ADC2, and the six lsb of the third data is inverted to emulate ADC3. When the FIFO test is enabled, a total of three data words are stored in the FIFO, one of which is a write instruction. In order to fill the entire FIFO register with test data, 10 writes must be performed. Test data is written to the FIFO only when the four enable bits have the AH value. This register should not be used in normal operation.

Comparator Test Register (25H)

The purpose of the comparator test register at address 25H is to apply the defined pattern to the comparator output pins. This function is used to test algorithms in DSPs or hardware controlled by comparator outputs. To enable the comparator test, the enable section of the register must contain the value 0CH. This register should not be used in normal operation. By reading the comparator test register, the comparator output is sent back to allow the host to read the actual comparator output within one cycle.

Interrupt Register (26H)

The interrupt register at address 26H contains the interrupt source and interrupt control bits. Bits xOxF are set when a particular counter has overcurrent or undercurrent. The bit remains set until the interrupt register is read; this is independent of whether the counter's overcurrent or undercurrent state remains. Counter overcurrent or undercurrent interrupts are enabled when the appropriate xOxE bits are set.

The FFF bit FIFO full flag will be set when the FIFO is full (or full) and will remain set until the interrupt register is read, regardless of whether the FIFO is full or not. The FF bit FIFO full indicates whether the FIFO is full. When reading the interrupt register, the FFF bit is cleared. The FIFO full interrupt is enabled when bit FFE (or FIFO full enable) is set.

The FEF bit FIFO empty flag will be set when the FIFO is (or was) empty and will remain set until the interrupt register is read, regardless of whether the FIFO is empty or not. The FE bit FIFO empty indicates whether the FIFO is empty. Bit FEF is cleared when the interrupt register is read. When the fee bit FIFO empty enable is set, the FIFO empty interrupt is enabled. See the Interrupts section for more information on interrupt pins. Table 1-24 describes the interrupt registers.

Parallel register (27H)

The parallel register at address 27H controls the parallel interface mode 11; see the Mode 11 Bus Access section. Parallel registers have no effect on modes 00, 01 and 10. There is only one bit in the parallel register, the M bit.

Reset register (28H)

The reset register at address 28H can fully reset the ADS7869 or simply reset the counter. Writing the AAH mode to the CX bit will reset Counter 1 and Counter 2 and all registers associated with the counter. Writing the AAH mode to the SX bits will force the ADS7869 into a reset state; both the digital and analog sections are reset. The reset register is a write-only register. If the reset register is read, data 0000H will be received. The format of the input word is shown in Table 1-26. To reset the entire ADS7869, mode AAAAH should be written to the reset register.

Once the reset register activates a system reset, the register must not be rewritten to deactivate the reset condition. Writing another pattern to the CX bit (other than AAH) will deactivate the reset condition of the counter or the reset condition of the device.

See the Reset section for details on reset conditions.

first in first out

The FIFO of the ADS7869 is organized as a 32-word ring buffer of 16 bits per word, as shown in Figure 1-20. The converted ADS7869 data is automatically written to the FIFO. To control the writing and reading process, write pointers and read pointers are used. The read pointer always shows the position containing the last read data. The write pointer indicates the location containing the last written sample. The converted values are written to the circular buffer in a predefined order, starting with ADC1 and ending with ADC3. The channel number is stored with the ADC data. The FIFO data is read through the FIFO register at address 00H; its format is shown in Table 1-27. The table shows that channel information for converted channel data is maintained continuously. Address 00H in the register map only shows the data pointed to by the read pointer.

The FIFO generates the DAV signal; Figure 1-22. In VECANA mode, this signal is low; indicating that the ADS7869 is converting data. In other modes, DAV indicates that the data in the FIFO is available. DAV signals can be configured as positive or negative; see the Control Registers section.

When the write pointer is before the read pointer, the DAV signal becomes active. When the read pointer equals the write pointer (ie, when the FIFO is empty), the DAV signal becomes inactive again.

When the ADC writes data into the FIFO, and the write pointer is more than 32 steps ahead of the read pointer, the FF (FIFO Full) state is set. FF is cleared when the first FIFO read operation is performed. To synchronize the pointer after the FF state, the FIFO should be read until FE occurs (FIFO empty).

If a read is attempted and the read and write pointers are equal, the read pointer will not be incremented; the same data (data with the same channel number) will be read again. When this happens, an FE state is set. The FE state is cleared when new data is written to the FIFO. The read pointer does not exceed the write pointer. Both FF and FE go into the interrupt section. The functional block diagram of the FIFO is shown in Figure 1-21.

The purpose of the test data is to verify the FIFO structure for application development. This is described in the FIFO Test Registers section. This register should not be used in normal operation.

DAV Timing Characteristics

Exceeds the recommended operating free air temperature range of -40°C to +85°C, Avg=5V, BV=3V−5V.

Digital Counter Module

The ADS7869 interface for analog position sensors has the following features:

(1), the highest operating frequency of 16MHz;

(2) Error-safe state machine for full four-quadrant decoding • High noise immunity:

- Differential signal input

- Analog input comparator with hysteresis

- Schmitt-triggered digital inputs: digital noise filter; 16-bit binary up/down counter with overcurrent and undercurrent detection; synchronous to system clock; asynchronous and synchronous latching of counter value while sampling and holding ADC value ; five shadow registers.

operate

Analog position sensors have two signals at the output, sine and cosine. Both signals are differential and are positioned 90 degrees from each other. The sign comparator typically has a hysteresis of 75mV and processes the differential signal output by the position sensor. This greatly reduces common mode noise in motor control applications. The digital output signal of the comparator is connected to the counter input. Use a Schmitt trigger input for additional noise rejection. Digital signals are transmitted through programmable digital filters. The filtered no-fault signals are processed by a state machine, which increments or decrements a counter. The counter value is then latched into the corresponding register via the synchronous or asynchronous hold signals HOLD1 and HOLD2.

There is one counter module for each pair of position sensor signals (A1, B1 and A2, B2). These counters can count up or down, depending on the direction of the position sensor signal (ie, the phase difference of signals A1 and B1 or A2 and B2, respectively). These counter values are stored in shadow registers when the ADC channel is sampled and held. The four position sensor channels and counter values are sampled simultaneously on the HOLD1 or HOLD2 signal.

Using a system clock of 16MHz, the maximum data rate of the counter is 2MHz.

digital noise filter

The digital noise filter suppresses noise on the input quadrature signal. Digital noise filters suppress large, short-duration noise spikes; spurious counts triggered by noise or spikes are also significantly suppressed. See Figure 1-24.

The input signal CntXY is sampled on the rising clock edge. The signal must be stable for at least three consecutive rising clock edges before it is passed to the state machine. Pulses shorter than two clock periods are rejected; glitches between rising clock edges are also ignored. See Figure 1-25.

Filter Timing Characteristics (1)

Exceeds the recommended operating free air temperature range of -40°C to +85°C, Avg=5V, BV=3V−5V.

Binary Counters and Registers

The complete up/down counter consists of two 16-bit counters and five 16-bit shadow registers. The first counter is a 16-bit up/down counter, which is based on the U/D signal. This is the rough corner counter and it's called EDGECNT. For fine angle calculations, a second 16-bit counter, TIMECOUNT, is implemented. This counter is incremented with the system clock and reset on edge signals. Unable to decrement the TIMECOUNT counter. The system is shown in Figure 1-27, and the timing is shown in Figure 1-28. The U/D signal is high, counting up, when B1 runs before A1. When A1 runs before B1, the U/D signal is low and counts down. The edge signal is set by each filtered edge of A1 and B1.

When EDGECNT causes overcurrent or undercurrent, the corresponding bit in the interrupt register is set. The counter continues to increment or decrement. When the edge signal rises, the time count value is locked in the shadow register edgepd. The value of edgepd is the number of system clocks between the two active edges of the comparator input signal. This value is proportional to the angular velocity of the position sensor. The value in the edgepd register is locked in SYEDGPRD and registered on the sync hold signal HOLD1.

The EDGECNT and TIMECOUNT counter values are stored in the shadow register (SYEDGCNT and the sync hold signal, HOLD1, which samples the analog input. The value of the SYEDGTIME register represents the time between the last edge signal and the sync hold signal to hold 1. The EDGECNT counter value is stored in the asynchronous hold 1. The sampled signal is held at 2.

The shadow registers SYEDGCNT, ASEDGCNT, SYEDGPRD, and SYEDGTIME can be read through the register map. The counter EDGECNT can be written to through the address of the SYEDGCNT register in the register map. The 14 msbs of written data are stored in the EDGECNT register. These two lsbs are determined by the inputs FiltA1 and FiltB1; see the Edge Count Register section. This is to prevent inconsistencies between the ADC data of the edge counter and the position sensor input signal.

interrupt

Interrupts can come from several sources:

(1), FIFO complete state

(2), FIFO empty state

(3), two overcurrent or undercurrent counts

(4), two edge count overcurrent or overcurrent

These six signal sources are combined into one interrupt signal. The interrupt signal is high; when the interrupt pin INT is high, one of the six sources is also high.

To reset an interrupt, the interrupt register (see the Interrupt Registers section) must be read so the host can determine which source or sources caused the interrupt.

reset

The ADS7869 can be forced into a reset state in three different ways:

(1), turn on the power.

(2) Pull down the RST pin (reset pin 79).

(3), write the reset register.

In addition, the digital counter can be reset by the reset register without resetting the entire ADS7869.

In the reset state, the analog inputs are sampled, the registers (in the register map) are forced to their reset values, and the FIFOs and counters are cleared. In the reset condition, a rising clock pulse is required to reset the synchronous counter.

The ADS7869 requires one clock cycle to begin normal operation after the last reset condition is cleared. (See Figure 1-29.)

Reset Timing Characteristics

Exceeds the recommended operating free air temperature range of -40°C to +85°C, Avg=5V, BV=3V−5V.