Features

1. Overview

1.1 Outline of Specifications

1.2 List of Products

1.3 Block Diagram

1.4 Pin Assignments

1.5 Pin Functions

2. CPU

2.1 General-Purpose Registers (R0 to R15)

2.2 Control Registers

3. Address Space

3.1 Address Space

4. I/O Registers

4.1 I/O Register Addresses (Address Order)

4.2 I/O Register Bits

5. Electrical Characteristics

5.1 Absolute Maximum Ratings

5.2 DC Characteristics

5.3 AC Characteristics

5.3.1 Clock Timing

5.3.2 Control Signal Timing

5.3.3 Timing of On-Chip Peripheral Modules

5.3.4 Timing of PWM Delay Generation Circuit

5.4 A/D Conversion Characteristics

5.5 Power-on Reset Circuit, Voltage Detection Circuit Characteristics

5.6 Oscillation Stop Detection Timing

5.7 ROM (Flash Memory for Code Storage) Characteristics

5.8 Data Flash (Flash Memory for Data Storage) Characteristics

Appendix 1. Package Dimensions

REVISION HISTORY

Datasheet R01DS0096EJ0200 Rev.2.00 January 10, 2014 Page 1 RX62T Group, RX62G Group Renesas MCU Features 32-bit rx cpu core? Max. Operating frequency: 100 MHz 165 DMIPS operating at 100 MHz? Single-precision 32-bit IEEE-754 floating point? The accumulator handles 64-bit results (for a single instruction) from 32-x32-bit operations. Multiply and divide unit handles 32-×32-bit operations (multiply instruction takes one CPU clock cycle)? Fast interrupts? Divider (fastest instruction execution takes two CPU clock cycles)? Fast interrupts? csc Harvard architecture with 5-stage pipeline? Variable-length instructions: ultra-small code? Supports memory protection unit (Mpu),? Background jtg debugging and high-speed tracing. Operating voltage? Single supply 3.3V or 5-V power supply; 5V analog supply is possible with 3.3-V products Low power design and architecture? Four low power modes on-chip main flash, no wait states? 100-mhz operation, 10 ns read cycle? No wait states for full-speed reads? 64-Kbyte/128-Kbit/256-Kbyte capacity? For instructions and operands? User code, programmed via SCI or JTAG. On-chip data flash memory? Max.32K bytes, reprogrammable up to 30,000 times? Erase and program impose no burden on the cpu. On-chip SRAM, no wait states. 8-K bytes/16-byte SRAM for instructions and operands External crystal oscillator or internal phase-locked loop 8 to 12.5 MHz? Internal 125 kHz detection of iwdt for main oscillator stop? (Iec 60730 compliance) Independent watchdog timer (IEC 60730 compliance) 125-kHz clock operation ? Software cannot block robust WDT. Up to 7 co communication interfaces ? 1: CAN (ISO 11898-1 compliant) with 32 mailboxes ? 3: SCIS with asynchronous mode (including noise), clock synchronous mode and smart card interface mode . ?1: I2C bus interface, executable ?1: RSPI ?1: LIN operation up to 16-bit timer ?8: 16-bit MTU 3: 100 MHz operation, input capture, output compare, two three-phase complementary pwm output channels, The complementary pwm has no load on the cpu, and the phase counts. ?4: 16-bit gpt: 100MHz operation, input capture, output compare Four complementary single-phase pwm output channels, or one three-phase complementary pwm output channel and one single complementary pwm output channel, complementary pwm applies no load to the cpu , connected to the comparator for operation (for counting and controlling the negative pwm signal) to detect abnormal oscillation frequency (according to iec 60730 standard). ? 4: Generation of delay in 16-bit cmtPWM waveform (for (RX62G group only) ? Rise and fall of timing output pin of signal on 16-bit GPTPWM can be controlled with accuracy up to 312 ps (in 100 MHz operation). 3 1 A/D conversion unit for 1 MHz operation, a total of 20 channels , Dual Data Register, Amplifier, Comparator 12: Single 10-bit adc unit Cyclic Redundancy Check (CRC) calculation unit Monitoring of data being transmitted (for IEC 60730 compliance) Monitoring of data in memory (for IEC 60730) comply with )) not more than 61 input and output ports and a maximum of 21 input ports. Port? Port Register: Monitoring of output ports (for IEC 60730 compliance) operating temperature. Range?-40?C to +85?C?-40?C to +105?CPLQP0112JA-A20×20 mm, 0.65mm pitch-A14×14 mm, 0.5mm pitch -A 10×10 mm, 0.5mm pitch PLQP0064GA-A14x14 mm, 0.8mm pitch? -40?C to +85?C? -40?C to +105?C 100-MHz 32-bit RX MCU, FPU, 165 DMIPS, 12-bit ADC (3S/H circuit, dual data register, amplifier, comparator): two units, one unit for 10-bit ADC, three ADC units can realize 7-ch at the same time. Sampling, 100 MHz PWM (Two-Phase Complementary Channels and Four Single-Phase Complementary Channels or Three-Phase Complementary Channels and One Single-Phase Complementary Channel) R01DS0096EJ0200 Rev.2.00 Jan 10, 2014 Page 1 Rev.2.00 2014 January 10